Wafer‐Scale Split‐Channel a‐IGZO TFTs for Hump‐Free and Stress‐Robust Operation

ABSTRACT Amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs) have emerged as a key backplane technology for advanced displays because of their high mobility, large‐area uniformity, and low‐temperature processability. Despite their widespread adoption, however, the anomalous hump phenomenon—manifested as a two‐step turn‐on behavior that degrades switching performance and circuit stability—remains a significant reliability challenge. In this work, we present a comprehensive investigation into the physical origin of this issue. Through a combination of electron energy‐loss spectroscopy (EELS) and 3D Technology Computer‐Aided Design (TCAD) simulations, we confirm that the hump is caused by an edge effect, where plasma‐induced oxygen vacancies at the channel edge regions create a parasitic conduction path. To address this, we propose and demonstrate a novel split‐channel architecture that divides the main channel into multiple narrow subchannels. This design not only completely eliminates the hump but also significantly enhances performance, achieving a 90.72% increase in on‐current (I _on ) and a 47.90% reduction in contact resistance (R _c ). Furthermore, the split‐channel TFTs exhibit superior long‐term stability, preventing the hump from reappearing even under various operational stress conditions. Our findings provide both a fundamental understanding of this issue and a robust, scalable solution for the development of high‐performance oxide TFTs for next‐generation displays.