Wafer-scale fabrication of silicon nanowire arrays with controllable dimensions

Abstract A novel and facile method was successfully developed to fabricate wafer-scale Si nanowire arrays with well-controlled sizes through the in-situ porous anodic alumina (PAA) template-assisted wet-etching process. The diameter and filling ratio (inter-wire spacing) of the as-prepared Si nanowires are determined by the size and density of pores in the in-situ PAA templates, which can be tailored independently by adjusting the anodization voltages and the immersion time of PAA templates in phosphoric acid. The length of Si nanowires can be more than one hundred micrometers long, which is controlled by adjusting the wet-etching time. Moreover, this method is compatible with complex Si surface topology for creating desirable 3-dimensional hybrid micro/nano-structures. Such Si nanowire arrays exhibit ultralow reflectance and interesting wettability that are of great importance to photovoltaics and thermal management applications.