Development of low-temperature bonding platform using ultra-thin area selective deposition for heterogeneous integration
Source abstract
Abstract
The Cu-Cu bonding technology is an indispensable vehicle for achieving heterogeneous integration, providing architects and designers with a new solution to address the limitations of transistor miniaturization. In this study, a next-generation efficient-process passivation bonding technology has been developed and investigated. The area-selective passivation bonding platform enables chips to be bonded at ambient temperatures below 200 ℃, while mitigating potential patterning issues and simplifying the complex conventional passivation process. The surface exploration of the area-selective films and their bonding mechanism have been thoroughly investigated through the use of transmission electron microscope (TEM) analyses. The results demonstrate exceptional film quality and the bonded reliability of the area-selective films. Furthermore, devices bonded using an optimized process exhibit more reliable mechanical strength than those bonded using conventional passivation methods.
Source: openalex_inverted_index · Quality: baseline
Research context
OpenAlex topics: 3D IC and TSV technologies · Electronic Packaging and Soldering Technologies · Additive Manufacturing and 3D Printing Technologies
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
References (37)
Show source-provided references
1. Heterogeneous Integration Enabled by the State-of-the-Art 3DIC and CMOS Technologies: Design, Cost, and Modeling
2. S. Y. Hou, H. Hsia, C.H. Tsai, K.C. Ting, T.H. Yu, Y.W. Lee, F.C. Chen, W.C. Chiou, C.T. Wang, C.H. Wu, Douglas Yu, “Integrated Deep Trench Capacitor in Si Interposer for CoWoS Heterogeneous Integration,”2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019, pp. 19.5.1-19.5.4, https://doi.org/10.1109/IEDM19573.2019.8993498.10.1109/IEDM19573.2019.8993498 ↗
3. 3D SoC integration, beyond 2.5D chiplets
4. M. Chen, C. Lin, E. Liao, W. Chiou, C. Kuo, C. Hu, C. Tsai, C. Wang, D. Yu, SoIC for low-temperature, multi-layer 3D memory integration, in: 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), IEEE, 2020, pp. 855-860. https://doi.org/10.1109/ECTC32862.2020.00139.10.1109/ECTC32862.2020.00139 ↗
5. A. Agrawal, S. Huang, G. Gao, L. Wang, J. DeLaCruz, L. Mirkarimi, Thermal and electrical performance of direct bond interconnect technology for 2.5 D and 3D integrated circuits, in: 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), IEEE, 2017, pp. 989-998. https://doi.org/10.1109/ECTC.2017.341.10.1109/ECTC.2017.341 ↗
6. Lau · 2021
7. Reliability of key technologies in 3D integration10.1016/j.microrel.2012.08.011 ↗
8. Recent progress in transient liquid phase and wire bonding technologies for power electronics10.3390/met10070934 ↗
9. A review on recent advances in transient liquid phase (TLP) bonding for thermoelectric power module10.1515/rams-2018-0011 ↗
10. Controlling interfacial exchanges in liquid phase bonding enables formation of strong and reliable Cu–Sn soldering for high-power and temperature applications10.1021/acsaelm.0c01040 ↗
11. Low temperature transient liquid phase bonded Cu-Sn-Mo and Cu-Sn-Ag-Mo interconnects–A novel approach for hybrid metal baseplates10.1016/j.microrel.2018.06.051 ↗
12. C.-J. Zhan, C.-C. Chuang, J.-Y. Juang, S.-T. Lu, T.-C. Chang, Assembly and reliability characterization of 3D chip stacking with 30μm pitch lead-free solder micro bump interconnection, in: 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC), IEEE, 2010, pp. 1043-1049. https://doi.org/10.1109/ECTC.2010.5490829.10.1109/ECTC.2010.5490829 ↗
13. C.-J. Zhan, J.-Y. Juang, Y.-M. Lin, Y.-W. Huang, K.-S. Kao, T.-F. Yang, S.-T. Lu, J.H. Lau, T.-H. Chen, R. Lo, Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30μm pitch lead-free solder micro bumps and reliability characterization, in: 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), IEEE, 2011, pp. 14-21. https://doi.org/.10.1109/ECTC.2011.5898484 ↗
14. Effects of sulfide-forming element additions on the Kirkendall void formation and drop impact reliability of Cu/Sn–3.5 Ag solder joints10.1016/j.actamat.2009.06.060 ↗
15. Low-temperature Cu-Cu wafer bonding10.1149/05007.0139ecst ↗
16. Wafer-level Cu–Cu bonding technology10.1016/j.microrel.2011.04.016 ↗
17. Combined surface activated bonding technique for low-temperature Cu/dielectric hybrid bonding10.1149/2.0201607jss ↗
18. W. Yang, H. Shintani, M. Akaike, T. Suga, Low temperature Cu-Cu direct bonding using formic acid vapor pretreatment, in: 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), IEEE, 2011, pp. 2079-2083. https://doi.org/10.1109/ECTC.2011.5898804.10.1109/ECTC.2011.5898804 ↗
19. Effect of HF & H2SO4 pretreatment on interfacial adhesion energy of Cu–Cu direct bonds10.1016/j.mee.2011.06.002 ↗
20. D.F. Lim, J. Wei, C.M. Ng, C.S. Tan, Low temperature bump-less Cu-Cu bonding enhancement with self-assembled monolayer (SAM) passivation for 3-D integration, in: 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC), IEEE, 2010, pp. 1364-1369. https://doi.org/10.1109/ECTC.2010.5490639.10.1109/ECTC.2010.5490639 ↗
21. Effects of forming gas plasma treatment on low-temperature Cu–Cu direct bonding10.7567/JJAP.55.06JC02 ↗
22. D.F. Lim, J. Wei, C.M. Ng, C.S. Tan, Low temperature bump-less Cu-Cu bonding enhancement with self-assembled monolayer (SAM) passivation for 3-D integration, in: 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC), IEEE, 2010, pp. 1364-1369. https://doi.org/10.1109/ECTC.2010.5490639.10.1109/ECTC.2010.5490639 ↗
23. Investigation of Low-Temperature Cu–Cu Direct Bonding With Pt Passivation Layer in 3-D Integration10.1109/TCPMT.2021.3069085 ↗
24. Demonstration of Low-Temperature Fine-Pitch Cu/SiO₂ Hybrid Bonding by Au Passivation10.1109/JEDS.2021.3114648 ↗
25. Electrical and Reliability Investigation of Cu-to-Cu Bonding With Silver Passivation Layer in 3-D Integration10.1109/TCPMT.2020.3037365 ↗
26. Low Temperature Copper-Copper Bonding of Non-Planarized Copper Pillar with Passivation10.1109/LED.2020.3001163 ↗
27. Investigation of bonding mechanism for low-temperature Cu-Cu bonding with passivation layer10.1016/j.apsusc.2022.153243 ↗
28. I.A. Weng, H.T. Hung, S. Yang, C.R. Kao, Y.H. Chen, Self-assembly of reduced Au atoms for vertical interconnections in three dimensional integrated circuits, Scripta Materialia, Volume 159, 2019, Pages 119-122, ISSN 1359-6462, https://doi.org/10.1016/j.scriptamat.2018.09.026.10.1016/j.scriptamat.2018.09.026 ↗
29. L.Y.H.T. Kao, Y.H. Chen, & C.R. Kao, Bonding of Copper Pillars Using Electroless Cu Plating, in: 2019 International Conference on Electronics Packaging (ICEP), IEEE, 2019. Pp. 220-222, https://doi: 10.23919/ICEP.2019.8733511.10.23919/ICEP.2019.8733511 ↗
30. Development of high copper concentration, low operating temperature, and environmentally friendly electroless copper plating using a copper - glycerin complex solution10.1016/j.electacta.2022.140710 ↗
31. Native oxide formation on pentagonal copper nanowires: A TEM study10.1016/j.susc.2018.03.005 ↗
32. Grain-boundary diffusion and segregation of gold in copper: Investigation in the type-B and type-C kinetic regimes10.1103/PhysRevB.50.3577 ↗
33. A. Aleshin, B.S. Bokstein, V. Egorov, P. Kurkin, Grain boundary and bulk diffusion in Au-Cu thin films, in: Defect and Diffusion Forum, Trans Tech Publ, 1993, pp. 457-462. https://doi.org/10.4028/www.scientific.net/DDF.95-98.457.10.4028/www.scientific.net/DDF.95-98.457 ↗
34. Mechanisms of interdiffusion in Pd–Cu thin film diffusion couples10.1016/j.tsf.2009.08.026 ↗
35. Evolution of concentration profiles in Pd–Cu systems studied by SNMS technique10.1016/j.vacuum.2013.04.015 ↗
36. Analytical methods used for low temperature Cu–Cu wafer bonding process evaluation10.1007/s00542-015-2446-2 ↗
37. Zhong-Jie Hong, Demin Liu, Han-Wen Hu, Chien-Kang Hsiung, Chih-I Cho, Chih-Han Chen, Jui-Han Liu, Ming-Wei Weng, Mu-Ping Hsu, Ying-Chan Hung, Kuan-Neng Chen, Low-temperature hybrid bonding with high electromigration resistance scheme for application on heterogeneous integration, Applied Surface Science 610 (2023) 155470. ISSN 0169-4332, https://doi.org/10.1016/j.apsusc.2022.155470.10.1016/j.apsusc.2022.155470 ↗