A novel computing-in-memory array based on STT-MRAM using high on–off ratio 2T-1M bit-cell
Source abstract
Abstract
With the rapid advancement of artificial intelligence (AI) and the explosion of data, there is an increasingly urgent demand for computing-in-memory technology. This paper introduces an innovative computing-in-memory array and its application in edge AI inference based on spin-transfer-torque magnetoresistance random access memory. The bit-cell of this array is composed of two transistors and one magnetic tunnel junction (2T-1M), which greatly improves the on/off ratio to 50 at a sampling frequency of 23 MHz, which is 25 times larger than a conventional cell. Correspondingly, the current rate of change is employed instead of the current magnitude in a conventional array. We also explore the non-idealities, including sampling frequency and resistance variation, which indicates that the proposed array maintains better stability. The array performs image classification using the MNIST dataset and achieves an accuracy of 96.3%, which is approximately equivalent to the accuracy of software. Finally, the 2T-1M array achieves a 48.8% lower energy consumption compared to the conventional 1T-1M array at a size of 64 (rows) × 64 (columns).
Source: crossref · Quality: baseline
Research context
OpenAlex topics: Magnetic properties of thin films · Ferroelectric and Negative Capacitance Devices · Advanced Memory and Neural Computing
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
State Key Laboratory of Spintronics Devices and Technologies , Hangzhou, Zhejiang 311305,
References (35)
Show source-provided references
1. IEEE Trans. Cybern. · 2019 · 49 · 108410.1109/tcyb.2018.2795041 ↗
2. IEEE Trans. Emerg. Top. Comput. Intell. · 2018 · 2 · 4110.1109/tetci.2017.2772792 ↗
3. Proc. IEEE · 2020 · 108 · 124510.1109/jproc.2019.2897076 ↗
4. IEEE Trans. Comput. · 2020 · 69 · 99810.1109/tc.2020.2982159 ↗
5. Towards energy efficient non-von neumann architectures for deep learning
6. IEEE Trans. Circuits Syst. I · 2021 · 68 · 275310.1109/tcsi.2021.3072200 ↗
7. 29.1 a 40 nm 64 Kb 56.67 TOPS/W read-disturb-tolerant compute-in-memory/digital RRAM macro with active-feedback-based read and in-situ write verification
8. Monolithic 3D integration of high endurance multi-bit ferroelectric FET for accelerating compute-in-memory
9. IEEE Electron Device Lett. · 2022 · 43 · 30410.1109/led.2021.3139574 ↗
10. IEEE J. Explor. Solid-State Comput. Devices Circuits · 2020 · 6 · 3610.1109/JXCDC.2020.2992228 ↗
11. Recent progresses in STT-MRAM and SOT-MRAM for next generation MRAM
12. Improving write performance for STT-MRAM10.1109/tmag.2016.2541629 ↗
13. A 14 nm embedded STT-MRAM CMOS technology
14. Highly functional and reliable 8Mb STT-MRAM embedded in 28 nm logic
15. A 14 nm MRAM-based multi-bit analog in-memory computing with process-variation calibration for 72 macros-based accelerator10.1109/lssc.2024.3465595 ↗
16. A 40 nm 4 Mb high-reliability STT-MRAM achieving 18 ns write-time and 94.9% wafer-level-die-yield across -55 °C-to-125 °C
17. Overview of reliability in scaling embedded STT-MRAM
18. In-memory computing in emerging memory technologies for machine learning: An overview
19. Efficient in-memory computing architecture based on crossbar arrays
20. A crossbar-based in-memory computing architecture10.1109/tcsi.2020.3000468 ↗
21. Crossbar-based memristive logic-in-memory architecture10.1109/tnano.2017.2691713 ↗
22. Compute-in-memory chips for deep learning: Recent trends and prospects10.1109/mcas.2021.3092533 ↗
23. A variation robust inference engine based on STT-MRAM with parallel read-out
24. A crossbar array of magnetoresistive memory devices for in-memory computing10.1038/s41586-021-04196-6 ↗
25. A maximally row-parallel MRAM in-memory-computing macro addressing readout circuit sensitivity and area
26. SRIF: Scalable and reliable integrate and fire circuit ADC for memristor-based CIM architectures10.1109/tcsi.2021.3061214 ↗
27. 33.4 A 28 nm 2 Mb STT-MRAM computing-in-memory macro with a refined bit-cell and 22.4 - 41.5 TOPS/W for AI inference
28. X-fault: Impact of faults on binary neural networks in memristor-crossbar arrays with logic-in-memory computation
29. A 40 nm 100 Kb 118.44 TOPS/W ternary-weight compute-in-memory RRAM macro with voltage-sensing read and write verification for reliable multi-bit RRAM operation
30. Secure XOR-CIM engine: Compute-in-memory SRAM architecture with embedded XOR encryption10.1109/tvlsi.2021.3120296 ↗
31. Secure-RRAM: A 40 nm 16 Kb compute-in-memory macro with reconfigurability, sparsity control, and embedded security
32. Deep residual learning for image recognition
33. Novel highly scalable multi-level cell for STT-MRAM with stacked perpendicular MTJs
34. A 40 nm RRAM compute-in-memory macro featuring on-chip write-verify and offset-cancelling ADC references
35. STT-MRAM design technology co-optimization for hardware neural networks