Static characteristics of CMOS digital circuit based on transition metal dichalcogenide transistors

Static characteristics of digital combinational logic circuits and Schmitt triggers based on two-dimensional (2D) transition metal dichalcogenides (TMDs) have been systematically explored. Selenide tungsten (WSe2) transistors act as the P type metal oxide semiconductor (PMOS). Molybdenum disulfide (MoS2) transistors play the role as N type metal oxide semiconductor (NMOS). Based on the circuit simulations, we find that the output of the complementary metal oxide semiconductor (CMOS) inverters and Schmitt triggers can approach the supply voltage (VDD) and ground (GND), respectively. The key performance indexes of the two digital circuits have been studied with the change of the device parameters. The simulation results indicate that a thinner gate oxide thickness and a higher dielectric permittivity gate oxide material can increase the noise margin of the inverters. Besides, different width ratios of PMOS and NMOS can influence the noise margin of inverters. An inverter with a large PMOS whose width is 64 nm and a small NMOS whose width is 32 nm can improve the low level noise margin, but reduce the high level noise margin. In addition, a gate oxide thickness of 2.8 nm can broaden the hysteresis window of the Schmitt triggers obviously. The output curves of the Schmitt triggers change slightly with different gate oxide materials. The hysteresis window of the Schmitt triggers becomes narrow with decreasing of the supply voltage. The present work could help to design the standard cells with different requirements and improve the performance of digital integrated circuits using TMDs transistors.