journal article·2015-04-01Open access

The demonstration of a D-SMT stressor on Ge planer n-MOSFETs

M.-H. Liao, P.-G. Chen

AIP Advances· Volume 5· Issue 4

Abstract

An approximately 31% Id,sat improvement and 42% mobility enhancement are achieved on the planer Ge n-Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) by implementing the dislocation-stress memorization technology (D-SMT) stressor for the first time, based on an investigation of crystal re-growth velocities along different directions and the optimization of the dislocation angle (θ) in Ge. Ultra-high stress (>3 GPa) capping SiN film is found to be essential for modifying the crystal re-growth velocities along the [100] and [110] directions to optimize the θ. The change of crystal re-growth velocities and the mobility enhancement ratio with the stress along the assigned directions in Ge is also discussed, respectively.
Source: crossref · Quality: baseline

Research context

OpenAlex topics: Semiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Advanced Surface Polishing Techniques

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

Affiliations

National Taiwan University Department of Mechanical Engineering, , Taipei, Taiwan, R. O. C. , 10617

Funding

National Science Council

References (13)

Show source-provided references
1. Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-kmetal gate devices
2. Modeling of NMOS Performance Gains from Edge Dislocation Stress
3. Molecular Dynamic Simulation Study of Stress Memorization in Si Dislocations
4. The demonstration of D-SMT stressor on Si and Ge n-FinFETs
5. Modeling and Optimization of Edge Dislocation Stressors10.1109/LED.2013.2266124 ↗
6. Stressed multidirectional solid-phase epitaxial growth of Si10.1063/1.3091395 ↗
7. The systematic study and simulation modeling on nano-level dislocation edge stress effects
8. Substrate orientation dependence on the solid phase epitaxial growth rate of Ge
9. Oxygen Potential Engineering of Interfacial Layer for Deep Sub-nm EOT High-k Gate Stacks on Ge
10. Phys. Rev. B · 1991 · 44 · 981210.1103/PhysRevB.44.9812 ↗
11. 1948
12. Microelectronics Engineering · 2015 · 138 · 1210.1016/j.mee.2015.01.013 ↗
13. Appl. Phys. Lett. · 2007 · 91 · 10210310.1063/1.2779845 ↗