Fully tensile strained partial silicon-on-insulator n-type lateral-double-diffused metal-oxide-semiconductor field effect transistor using localized contact etching stop layers

The use of contact etching stop layer (CESL) stressors is a popular technique for introducing stress into a transistor channel. However, when tensile stress is applied to an n-type lateral double-diffused metal-oxide-semiconductor (LDMOS) by covering the whole device with a CESL, the drift region adjacent to the channel will be compressively strained, which is detrimental to device performance. The current work presents a strained partial silicon-on-insulator LDMOS in which tensile stress was introduced in both the channel and drift region via a CESL to reduce the device’s on-resistance and improve its frequency performance. An n-type LDMOS device with a top-layer Si thickness that was varied between 300 and 20 nm was simulated to investigate the effect of CESLs on device performance. Devices in which the channel and drift region were fully strained had larger carrier mobilities, and their cut-off frequencies were increased by 25% compared with a normal unstrained partial silicon-on-insulator LDMOS field effect transistor. Meanwhile stress was shown to have little impact on the breakdown voltage of the two types of LDMOS field effect transistor studied here.