Compact modeling of metal–oxide TFTs based on the Bayesian search-based artificial neural network and genetic algorithm

Thin-film transistors play an important role in ultra-high definition displays. The conventional physical model requires a significant amount of time and resources, while its generalizability is limited. This paper introduces a method for quickly incorporating the characteristics of emerging devices into circuit simulations using an artificial neural network (ANN) model. The multi-layer perceptron (MLP) model, with a simple structure and high modeling efficiency, is employed as a typical ANN model. The pivotal step in using the MLP model is to determine its topology. This hyperparameter problem can be easily solved using Bayesian search. To improve the accuracy of the model, a genetic algorithm is proposed to optimize the initial values of the weights and biases. Furthermore, by introducing the first derivative in the loss function, small signal parameters can be taken into consideration. This modeling approach significantly reduces the time required for compact device modeling. Our experimental results exhibit a strong correlation between the model’s output and the corresponding experimental data, thereby providing comprehensive validation for the effectiveness of our proposed model. Once the trained model parameters were extracted, we implemented the hybrid ANN model using Verilog-A. This circuit-level experiment demonstrates that this hybrid ANN model can accurately estimate various physical devices and circuits.