Design and investigation of dopingless dual-gate tunneling transistor based on line tunneling

The dopingless tunneling FET (DLTFET) has attracted more and more attention due to the reduction of process complexity comparing to traditional TFET with heavy doping source and drain regions. But the on-state current of conventional DLTFET is lower because its on-state current is only determined by point tunneling (PT) between source and channel. In this work, a new dual-gate DLTFET based on line tunneling (LT) is designed and studied by Sentaurus TCAD simulation tool. The on-state current and subthreshold swing (SS) of DLTFET are greatly improved by skillfully designing back gate engineering and bias. Applying this novel design, the line tunneling is created from channel bottom to channel top, which dramatically enhances tunneling area and tunneling current. So the on-state current of LT_DLTFET consists of point tunneling between source and channel as well as line tunneling in channel region. Comparing to the traditional PT_DLTFET based on Ge, the simulation results reveal that the on-state current of LT_DLTFET based on Ge is increased to 14.8μA/μm from 6.5μA/μm at Vg=1V and Vd=0.5V, and the average SS and minimum SS are decreased to 22.9mV/dec and 6.5mV/dec from 33.9 mV/dec and 9.5mV/dec, respectively. The LT_DLTFET is also proper to both Si and III-V materials. This design greatly promotes the application potential of DLTFET.