Ternary Logic Transistors Using Multi‐Stacked 2D Electron Gas Channels in Ultrathin Oxide Heterostructures (Adv. Sci. 6/2025)

Ternary Logic Transistors In article number 2410519, Tae Joo Park, Ji Hyeon Choi, Sang Woon Lee, and co-workers develop a novel and simple ternary logic transistor by stacking 2D electron gas channels. The cover highlights the ternary logic states of 0, 1, and 2, achieved through the sequential operation of the upper and lower channels, induced by the threshold voltage difference between the stacked channels.