Low‐κ Extension Doping for High‐Performance Carbon Nanotube Transistors: Toward High‐Speed, Energy‐Efficient Electronics

Abstract Carbon nanotubes (CNTs) present considerable potential as next‐generation logic switches owing to their ultra‐thin structure and exceptional electrical properties. Although recent advancements have achieved impressive direct current (DC) performance in individual devices, research on the architectural design of CNT‐based transistors remains limited. This gap is critical, as device architecture directly influences power consumption and switching speed at the circuit level. In particular, the balance between parasitic capacitance and resistance, key factors determining resistive‐capacitive (RC) delay, has not been thoroughly addressed. In this study, top‐gate CNT metal–oxide–semiconductor field‐effect transistors (MOSFETs) that employ a novel low‐κ extension doping technique are presented. This approach utilizes a stacked SiO _x /AlF _x layer (κ = 3.9 and 2.5) to enhance device performance while minimizing parasitic capacitance between the top gate and contact metal. The proposed approach improves the driving current by 8.4 times and reduces the total resistance by 85% when compared with CNT MOSFETs with undoped extensions. The doping level is tunable from 0.5 nm ⁻¹ to 0.59 nm ⁻¹ , with electrostatic doping driven by negative charges at the SiO _x ​/AlF _x interface. The benchmarking results demonstrate the record‐low κ‐value and physical thickness presented by the proposed approach, highlighting its potential for high‐performance, high‐speed applications.