Bottom‐Gate Approach for All Basic Logic Gates Implementation by a Single‐Type IGZO‐Based MOS Transistor with Reduced Footprint

Abstract Logic functions are the key backbone in electronic circuits for computing applications. Complementary metal‐oxide‐semiconductor (CMOS) logic gates, with both n‐type and p‐type channel transistors, have been to date the dominant building blocks of logic circuitry as they carry obvious advantages over other technologies. Important physical limits are however starting to arise, as the transistor‐processing technology has begun to meet scaling‐down difficulties. To address this issue, there is the crucial need for a next‐generation electronics era based on new concepts and designs. In this respect, a single‐type channel multigate MOS transistor (SMG‐MOS) is introduced holding the two important aspects of processing adaptability and low static dissipation of CMOS. Furthermore, the SMG‐MOS approach strongly reduces the footprint down to 40% or even less area needed for current CMOS logic function in the same processing technology node. Logic NAND, NOT, AND, NOR, and OR gates, which typically require a large number of CMOS transistors, can be realized by a single SMG‐MOS transistor. Two functional examples of SMG‐MOS are reported here with their analysis based both on simulations and experiments. The results strongly suggest that SMG‐MOS can represent a facile approach to scale down complex integrated circuits, enabling design flexibility and production rates ramp‐up.