Impact of ferroelectric polarization dynamics on thermal reliability in Ferro-FinFETs

This paper systematically investigates the thermal failure mechanisms of 14 nm Ferro-FinFETs using the TCAD tools, incorporating both Preisach and thermodynamic models. A comparative analysis under programming (+ 4 V, 100 ns) and erasing (− 4 V, 100 ns) conditions reveals distinct ferroelectric domain switching behaviors and their impact on heat generation and thermal distribution. Programming induces a net downward polarization in the gate dielectric, which enhances electron accumulation at the channel surface, turns the device on, and results in a local temperature increase from 371 K to 390 K. The effects of programming voltage (PV) and pulse width (PW) are further examined, showing that increasing PV (PW) from 3 V (10 ns) to 7 V (1 µs) raises the peak temperature from approximately 379 K (375 K) to 400 K (396 K). Concurrently, thermal hotspots migrate from the drain/channel junction toward the channel center, attributed to enhanced polarization, higher current density, and redistribution of the electric field. This thermal imbalance, under fixed boundary conditions, limits heat dissipation in the channel center. These findings highlight a trade-off between polarization-induced memory window enhancement and elevated thermal risk, providing valuable insights for the thermoelectric co-design and optimization of Ferro-FinFET-based memory devices.