Promotion of Processability in a p-Type Thin-Film Transistor Using a Se–Te Alloying Channel Layer

p-type thin-film transistors (pTFTs) have proven to be a significant impediment to advancing electronics beyond traditional Si-based technology. A recent study suggests that a thin and highly crystalline Te layer shows promise as a channel for high-performance pTFTs. However, achieving this still requires specific conditions, such as a cryogenic growth temperature and an extremely thin channel thickness on the order of a few nanometers. These conditions critically limit the practical feasibility of the fabrication process. Here, we report a high-performance pTFT incorporating a 60-nm-thick highly crystalline Se–Te alloyed channel layer, produced using pulsed laser ablation at room temperature. The Se 0.5 Te 0.5 alloy system enhances crystalline temperature and widens the band gap compared to a pure Te channel. Consequently, this approach results in a field-effect mobility of 3 cm 2 /V·s, with an on/off current ratio of 3 × 10 5, a subthreshold slope of 2.1 V/decade, and a turn-on voltage of 6.5 V, achieved through conventional annealing at 250 °C. To demonstrate its applicability in complementary circuit applications, we integrate a complementary-type inverter using a p-type Se 0.5 Te 0.5 TFT and an n-type Al-doped InZnSnO, demonstrating a high voltage gain of 12 and a low static power consumption of 17 nW. This suggests that the Se–Te alloyed channel approach paves the way to a more straightforward and cost-effective process for Te-based pTFT devices and their applications.