Current-Induced Evolving Mechanical Properties, Formation of Defects, and Interfacial Intermetallic Growth in the Interconnects Bonded with Au Wire

High Resolution Image Download MS PowerPoint Slide Continuously improving chip integration and increasing packaging density increase the risk of performance degradation and electromigration (EM) failure on the bonding interface during electrical transmission. While EM failure, as a time-accumulated failure, is one core challenge of semiconductor reliability and is particularly severe in highly integrated chips. However, the polarity differences existing in commercial devices and the evolving polarity characteristics of microscale bonding interfaces have not been well addressed. Therefore, this study describes the polarity effects of EM in a commercial chip-end Au–Al system and reveals the evolution of intermetallic compound (IMC) growth at bonding interfaces under high-density currents. An EM simulation model is developed to jointly analyze the influence of current-induced polarity effects on the evolution of material migration and IMC growth together with experimental results. Specifically, under the influence of the polarity effect, the thickness of the anode IMC layer is approximately twice as thick as that of the cathode. The IMC thickness on both sides is much thicker than the center under the influence of the size effect. Unlike previous studies, the IMC at the commercial bonding interface is mainly the Al 3 Au 8 phase in columnar crystal morphology and the α-AlAu 4 phase in nanocrystalline morphology, with the former being mainly located in the middle region of the IMC layer, while the latter is mainly located in the edge region of the IMC layer. Due to the overgrowth of the IMC layer, the tensile mechanical properties of the interface are degraded, and the failure mode transforms from a single neck fracture to a predominant joint detachment. This study complements and improves the research framework of Au/Al interface IMC at commercial chip joints and lays a theoretical foundation for the development of semiconductor chips toward high integration, high density, and high reliability.