journal article·2025-02-19Open access

Nonvolatile Reconfigurable Transistor via Ferroelectrically Induced Current Modulation

Daniele Nazzari, Lukas Wind, Masiar Sistani, Dominik Mayr, Kihye Kim, Viktor Wahler, Walter M. Weber

Abstract

High Resolution Image Download MS PowerPoint Slide New logic in memory (LiM) architectures, able to unify memory and logic functionalities into a single component, are highly promising for executing self-learning algorithms such as artificial neural networks (ANNs), with lower energy requirements. The multigated reconfigurable field effect transistor (RFET) is a novel type of logic device that can be fully reconfigured at run-time, promising to be a very versatile platform for logic applications. If equipped with a memory element, then it would represent the ideal building block for LiM-enabling hardware with embedded self-learning capabilities. To reach this goal, here we investigate the integration of a ferroelectric Hf 0.5 Zr 0.5 O 2 (HZO) layer onto dual top gated RFETs. We demonstrate that HZO polarization charges can be successfully employed to tune the height of the two Schottky barriers, influencing the injection behavior and allowing the selection of the majority carriers, thus defining the transistor mode and switching it between a fully p-type transport to a prevalently n-type one. Moreover, we show that the modulation strength is strongly dependent on the height of the pulse used to polarize the ferroelectric domains, allowing for the selection of different current levels. All the different achievable states show a good retention over time, owing to the stability of the HZO polarization. The limitations of the produced devices are discussed, alongside possible mitigation strategies. The presented results demonstrate that ferroelectric HZO can modulate the carrier injection across Schottky barriers in RFET devices. This approach paves the way for the future realization of a fully optimized nonvolatile RFET, an ideal building block for novel LiM hardware, enabling low-power circuits for ANN execution.
Source: openalex_inverted_index · Quality: baseline

Research context

OpenAlex topics: Ferroelectric and Negative Capacitance Devices · Semiconductor materials and devices · Advanced Memory and Neural Computing

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

Affiliations

Institute of Solid State Electronics, Technische Universität Wien, Gußhausstraße 25-25a, 1040 Vienna, Austria

Funding

Austrian Science Fund · Technische Universit?t Wien

References (45)

Show source-provided references
1. 10.1038/nature1453910.1038/nature14539 ↗
2. Strubell, E.; Ganesh, A.; McCallum, A. Energy and Policy Considerations for Deep Learning in NLP. 2019; http://arxiv.org/abs/1906.02243, arXiv:1906.02243 [cs].10.18653/v1/P19-1355 ↗
3. 10.1016/j.jpdc.2019.07.00710.1016/j.jpdc.2019.07.007 ↗
4. Horowitz M. · IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). 2014 · 2014 · 1010.1109/ISSCC.2014.6757323 ↗
5. 10.1038/nphys256610.1038/nphys2566 ↗
6. 10.1038/s41928-018-0092-210.1038/s41928-018-0092-2 ↗
7. 10.3390/jlpea1001000710.3390/jlpea10010007 ↗
8. 10.1038/s41565-020-0655-z10.1038/s41565-020-0655-z ↗
9. Li S. · Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture. New York, NY, USA, · 2017 · 28810.1145/3123939.3123977 ↗
10. Seshadri V. · Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture. Cambridge Massachusetts · 2017 · 27310.1145/3123939.3124544 ↗
11. 10.1038/nature0894010.1038/nature08940 ↗
12. 10.1088/0957-4484/23/30/30520510.1088/0957-4484/23/30/305205 ↗
13. 10.1038/s41928-022-00858-z10.1038/s41928-022-00858-z ↗
14. Breyer E. T. · 2017 IEEE International Electron Devices Meeting (IEDM). San Francisco, CA, · 2017 · 28.5.110.1109/IEDM.2017.8268471 ↗
15. 10.1126/sciadv.aau575910.1126/sciadv.aau5759 ↗
16. 10.1016/j.sse.2022.10838110.1016/j.sse.2022.108381 ↗
17. 10.1109/TED.2023.334636110.1109/TED.2023.3346361 ↗
18. 10.1007/978-3-030-53273-4_1410.1007/978-3-030-53273-4_14 ↗
19. 10.1002/aelm.20190124410.1002/aelm.201901244 ↗
20. 10.1021/acsami.1c0750510.1021/acsami.1c07505 ↗
21. 10.1039/C8NR07135G10.1039/C8NR07135G ↗
22. 10.1021/acsami.2c0459910.1021/acsami.2c04599 ↗
23. 10.1063/1.363405210.1063/1.3634052 ↗
24. Baldauf T. · 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS). · 2019 · 1
25. 10.1063/1.491670710.1063/1.4916707 ↗
26. Schroder D. K. · 200510.1002/0471749095 ↗
27. 10.1063/1.131063510.1063/1.1310635 ↗
28. 10.1088/1361-6463/abf67510.1088/1361-6463/abf675 ↗
29. 10.1063/1.234873510.1063/1.2348735 ↗
30. 10.1109/JPHOTOV.2016.264539910.1109/JPHOTOV.2016.2645399 ↗
31. 10.1016/j.mser.2014.11.00110.1016/j.mser.2014.11.001 ↗
32. 10.1143/APEX.3.06150110.1143/APEX.3.061501 ↗
33. 10.1103/PhysRevMaterials.6.09460410.1103/PhysRevMaterials.6.094604 ↗
34. 10.1016/j.mee.2011.03.09910.1016/j.mee.2011.03.099 ↗
35. 10.1186/s40580-023-00403-410.1186/s40580-023-00403-4 ↗
36. 10.1063/1.211942510.1063/1.2119425 ↗
37. 10.1109/TED.2004.83987810.1109/TED.2004.839878 ↗
38. 10.1016/j.mee.2007.04.09410.1016/j.mee.2007.04.094 ↗
39. Han J.-P. · 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Catal. No.03CH37407). Kyoto, Japan, · 2003 · 16110.1109/VLSIT.2003.1221135 ↗
40. 10.1109/JEDS.2022.317121710.1109/JEDS.2022.3171217 ↗
41. Lizzit D. · ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC). · 2021 · 21510.1109/ESSDERC53440.2021.9631764 ↗
42. 10.1039/D0NR07597C10.1039/D0NR07597C ↗
43. Toprasertpong K. · IEEE International Electron Devices Meeting (IEDM). 2019 · 2019 · 23.7.110.1109/IEDM19573.2019.8993664 ↗
44. Shao X. · IEEE International Memory Workshop (IMW). 2023 · 2023 · 1
45. 10.1109/JEDS.2024.335020910.1109/JEDS.2024.3350209 ↗