Enhanced Electrical Performance of InAs Nanowire Field-Effect Transistors Based on the Y₂O₃ Isolation Layer

Nanowire (NW) field-effect transistors (FETs) have great potential in next-generation integrated circuits. InAs NWs are suitable for N-type transistors because of their excellent electrical properties. However, unlike the Si/SiO 2 system, the loose and defective native oxide of InAs is unable to passivate the channel surface and serve as an efficient isolation layer (IL) in the gate stack. Here, we, for the first time, demonstrate that using a stable dielectric Y 2 O 3 to replace the native oxide IL can effectively passivate the NW surface, isolate the channel surface from high-k HfO 2, and improve the electrical properties of InAs NW FETs significantly. First, top-gate devices with Y 2 O 3 IL outperform the devices with native oxide or chemically generated oxide of InAs as the IL, exhibiting a small subthreshold swing (SS) of 77 mV/dec, a large on–off ratio, a high field-effect mobility (μ FE ) of 1845 cm 2 /V·s, and an extremely low interface trap density ( D it ) of 9.1 × 10 11 eV –1 cm –2 . Double-gate FETs with Y 2 O 3 IL also show excellent gate control (drain-induced barrier lowering (DIBL) down to 35 mV/V) and a high μ FE of 2711 cm 2 /V·s (the highest in the multigate structure). In addition, InAs NW FETs with Y 2 O 3 IL show greater stability after long-term air exposure than those with native oxide IL, demonstrating retained on–off ratio, DIBL, transconductance, and even smaller SS (from 89 to 77 mV/dec). Finally, the results of low-temperature measurement suggest that Y 2 O 3 IL can effectively improve interface qualities. Our results indicate that Y 2 O 3 /HfO 2 InAs NW FETs have great potential in digital units of integrated circuits for future nodes. Our strategy for improving the interface between InAs NW and the dielectric layer is also valuable for other III–V NW devices.