Study of High Performance Nanoscale Channel Length Vertical Transistors with a Self-Aligned Blocking Layer

A transistor design employing all vertically stacked components has attracted considerable attention due to the simplicity of the fabrication process and the high conductivity easily realized by achieving nanolevel short channel lengths with two-dimensional current paths. However, fundamental issues, specifically the blocking of the gate electrical field to the semiconductive channel layer and high leakage current at the “off” state, have impeded this configuration in becoming a major transistor design. To address these issues, it has been proposed to introduce a blocking layer (BL) with embedded hole structures and source electrode with embedded hole structures, enhancing gate field penetration and carrier modulation. The hole structure embedded in the source and the BL on the drain induced a desirable combined effect of gate field penetration and carrier pathway modulation. The align accuracy and the hole size difference between BL and source electrode were confirmed as the most important design parameters for high performance of a transistor. We therefore proposed a self-aligning lithography method using a built-in mask that allows high alignment accuracy between the source hole structure and the BL hole structure on the drain over a large area without a high-resolution process system. This method also enables easy and fast fabrication of nanoscale channels with high performance. This design resulted in a transistor with an output of 28 mA/cm 2 and an on–off ratio exceeding 10 6 at 1 mV of V DS . However, at 3 V of V DS, the off-current increased significantly due to short-channel effects in the all metal electrode design. To solve this issue, Fermi level-tunable graphene replaced metal electrodes, maintaining an off-current below 10 pA and an on–off ratio around 10 7 at 3 V. In addition, the device demonstrates robust electrical properties to light without any special treatment and is stable with a threshold voltage shift of less than 1 V under bias stress. This study demonstrates that the proposed vertical transistor design is a viable candidate as a new major transistor design for various applications.