Low-Voltage Graphene Interface-Engineered Organic Ferroelectric Tunnel Junction Devices

It has been indicated that the path forward for the widespread usage of ferroelectric ( FE ) materials may be considerably facilitated through the reduction of programming voltages to on-chip logic-compatible values of <1 V. Obstacles involve issues related to the scaling of the FE s to lower thickness as well as the presence of an interfacial layer (IL) between the high-permittivity FE and the substrate- resulting in wasted voltage across the IL. Here, we show how lower operating voltages along with a higher tunneling electroresistance (TER) could be achieved through IL engineering. We use piezoresponse force microscopy and fabricated ferroelectric tunnel junctions (FTJs) to show that ultrathin FE films deposited on single-layer graphene/Si can exhibit polarization switching at reduced voltages ∼0.8 V with significant TER as compared to directly depositing on Si.