Show source-provided references
11. Mistry, K.; Allen, C.; Auth, C.; Beattie, B.; Bergstrom, D.; Bost, M.; Brazier, M.; Buehler, M.; Cappellani, A.; Chau, R.; Choi, C. H.; Ding, G.; Fischer, K.; Ghani, T.; Grover, R.; Han, W.; Hanken, D.; Hattendorf, M.; He, J.; Hicks, J.; Huessner, R.; Ingerly, D.; Jain, P.; James, R.; Jong, L.; Joshi, S.; Kenyon, C.; Kuhn, K.; Lee, K.; Liu, H.; Maiz, J.; McIntyre, B.; Moon, P.; Neirynck, J.; Pae, S.; Parker, C.; Parsons, D.; Prasad, C.; Pipes, L.; Prince, M.; Ranade, P.; Reynolds, T.; Sandford, J.; Shifren, L.; Sebastian, J.; Seiple, J.; Simon, D.; Sivakumar, S.; Smith, P.; Thomas, C.; Troeger, T.; Vandervoorn, P.; Williams, S.; Zawadzki, K. A 45 nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging. IEEE International Electron Devices Meeting (IEDM): Washington, DC, USA, 2007; Vol. 10; pp 247–12250.
10.1109/IEDM.2007.4418914 ↗14. Trentzsch, M.; Flachowsky, S.; Richter, R.; Paul, J.; Reimer, B.; Utess, D.; Jansen, S.; Mulaosmanovic, H.; Muller, S.; Slesazeck, S.; Ocker, J.; Noack, M.; Muller, J.; Polakowski, P.; Schreiter, J.; Beyer, S.; Mikolajick, T.; Rice, B.A 28nm HKMG Super Low Power Embedded NVM Technology Based on Ferroelectric FETs. IEEE International Electron Devices Meeting (IEDM): San Francisco, CA, USA, 3–7 Dec.2016; pp 11.15.11–11.15.14.
10.1109/IEDM.2016.7838397 ↗15. Dünkel, S.; Trentzsch, M.; Richter, R.; Moll, P.; Fuchs, C.; Gehring, O.; Majer, M.; Wittek, S.; Müller, B.; Melde, T.; Mulaosmanovic, H.; Slesazeck, S.; Müller, S.; Ocker, J.; Noack, M.; Löhr, D. A.; Polakowski, P.; Müller, J.; Mikolajick, T.; Höntschel, J.; Rice, B.; Pellerin, J.; Beyer, S.A FeFET Based Super-low-power Ultra-fast Embedded NVM Technology for 22nm FDSOI and beyond. IEEE International Electron Devices Meeting (IEDM): San Francisco, CA, USA, 2–6 Dec. 2017.
10.1109/IEDM.2017.8268425 ↗16. Luo, Q.; Gong, T.; Cheng, Y.; Zhang, Q.; Yu, H.; Yu, J.; Ma, H.; Xu, X.; Huang, K.; Zhu, X.; Dona, D.; Yin, J.; Yuan, P.; Tai, L.; Gao, J.; Li, J.; Yin, H.; Long, S.; Liu, Q.; Lv, H.; Liu, M.Hybrid 1T e-DRAM and e-NVM Realized in one 10 nm Node Ferro FinFET Device with Charge Trapping and Domain Switching Effects. IEEE International Electron Devices Meeting (IEDM): San Francisco, CA, USA, 1–5 Dec. 2018; pp 2.6.1–2.6.4.
10.1109/IEDM.2018.8614650 ↗17. Florent, K.; Pesic, M.; Subirats, A.; Banerjee, K.; Lavizzari, S.; Arreghini, A.; Di Piazza, L. D.; Potoms, G.; Sebaai, F.; McMitchell, S. R. C.; Popovici, M.; Groeseneken, G.; Van Houdt, J. V.Vertical Ferroelectric HfO2 FET Based on 3-D NAND Architecture: Towards Dense Low-Power Memory. IEEE International Electron Devices Meeting (IEDM): San Francisco, CA, USA, 1–5 Dec. 2018; pp 2.5.1–2.5.4.
10.1109/IEDM.2018.8614710 ↗30. Bae, H.; Nam, S. G.; Moon, T.; Lee, Y.; Jo, S.; Choe, D. H.; Kim, S.; Lee, K. H.; Heo, J.Sub-ns Polarization Switching in 25nm FE FinFET toward Post CPU and Spatial-Energetic Mapping of Traps for Enhanced Endurance. IEEE International Electron Devices Meeting (IEDM): San Francisco, CA, USA, 12–18 Dec. 2020; p 31.
10.1109/IEDM13553.2020.9372076 ↗33. Ali T. · 2019 · 28.27.21
36. Zhu, W.Hafnium Oxide and Hafnium Aluminum Oxide for CMOS Applications. Ph.D. dissertation, Yale University, New Haven, CT, 2003. https://www.proquest.com/dissertations-theses/hafnium-oxide-aluminum-cmos-applications/docview/305285640/se-2 (accessed September 28, 2021).