Charge Trapping in Amorphous Dielectrics for Secure Charge Storage
Source abstract
Abstract
The fundamental scientific ingredient in the current information society is charge trapping in dielectric materials. The current data storage device known as NAND flash is based on charge trapping in silicon nitride, and it has been widely used in semiconductor processing. The growth of information in human society has incessantly driven storage devices with higher information density. The evolution of higher density NAND flash has been advanced based on memory cell stacking, which necessitates an upscaling of the dielectric constant of charge-trapping dielectrics in the future. In this study, we demonstrate that the amorphous phase is a prerequisite for secure charge trapping in future high-dielectric constant charge-trapping dielectric materials, in which a lower process temperature is required. Additionally, we demonstrate that a composition-graded dielectric thin film is a promising solution for the low-temperature fabrication of NAND flash.
Source: openalex_inverted_index · Quality: baseline
Research context
OpenAlex topics: Semiconductor materials and devices · Advanced Memory and Neural Computing · Copper Interconnects and Reliability
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
School of Electronic and Electrical Engineering, Hankyong National University, 327 Jungang-ro, Anseong-si, Gyeonggi-do 17579, Korea
Department of Energy Science, Sungkyunkwan University, 2066 Seobu-ro, Suwon-si, Gyeonggi-do 16419, Korea
Funding
National Research Foundation
References (39)
Show source-provided references
1. 10.1109/JSSC.2016.260429710.1109/JSSC.2016.2604297 ↗
2. 10.1109/led.2007.91538010.1109/led.2007.915380 ↗
3. 10.1109/ted.2004.82986110.1109/ted.2004.829861 ↗
4. Huo, Z.; Yang, J.; Lim, S.; Baik, S.; Lee, J.; Han, J.; Yeo, I. S.; Chung, U. I.; Moon, J. T.; Ryu, B. I. Band Engineered Charge Trap Layer for Highly Reliable MLC Flash Memory. 2007 IEEE Symposium on VLSI Technology; IEEE, 2007 Jun 12; pp 138–139.10.1109/VLSIT.2007.4339758 ↗
5. 10.1063/1.353155910.1063/1.3531559 ↗
6. 10.1016/j.tsf.2010.02.05510.1016/j.tsf.2010.02.055 ↗
7. 10.1016/j.matlet.2012.10.02410.1016/j.matlet.2012.10.024 ↗
8. 10.1063/1.346232110.1063/1.3462321 ↗
9. 10.1109/LED.2009.203411510.1109/LED.2009.2034115 ↗
10. 10.1116/1.217402110.1116/1.2174021 ↗
11. Choi S. · IEDM Tech. Dig. · 2008 · 925
12. Shin, Y.; Choi, J.; Kang, C.; Lee, C.; Park, K.T.; Lee, J.S.; Sel, J.; Kim, V.; Choi, B.; Sim, J.; Kim, D.; Cho, H.; Kim, K. A Novel NAND-type MONOS Memory using 63nm Process Technology for Multi-Gigabit Flash EEPROMs. IEDM Technical Digest, IEEE International Electron Devices Meeting; IEEE, 2005; pp 327–330.
13. 10.1143/jjap.45.321310.1143/jjap.45.3213 ↗
14. Lee, C.J., Choi, J.; Kang, C.; Shin, Y.; Lee, J.S.; Sel, J.; Sim, J.; Jeon, S.; Choe, B.I.; Bae, D.; Park, K.; Kim, K. Multi-Level NAND Flash Memory with 63 nm-node TANOS (Si-Oxide-SiN-Al2O3-TaN) Cell Structure. Digest of Technical Papers, Symposium on VLSI Technology; IEEE, 2006; pp 21-22.10.1109/VLSIT.2006.1705197 ↗
15. https://www.3dincites.com/2014/12/samsungs-3d-v-nand-flash-product-ceaselessly-marching/ (accessed December 9, 2014).
16. Lee, S. Y.; Park, J. Architecture of 3D Memory Cell Array on 3D IC. 2012 4th IEEE International Memory Workshop; IEEE, 2012 May 20 pp 1–3.10.1109/IMW.2012.6213640 ↗
17. Sugizaki, T.; Kobayashi, M.; Ishidao, M.; Minakata, H.; Yamaguchi, M.; Tamura, Y.; Sugiyama, Y.; Nakanishi, T.; Tanaka, H. Novel Multi-Bit SONOS Type Flash Memory Using a High-k Charge Trapping Layer. 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No. 03CH37407); IEEE, 2003 Jun 10 pp 27–28.
18. Tan, Y. N.; Chim, W. K.; Choi, W. K.; Joo, M. S.; Ng, T. H.; Cho, B. J. High-k HfAlO Charge Trapping Layer in SONOS-Type Nonvolatile Memory Device for High Speed Operation. IEDM Technical Digest, IEEE International Electron Devices Meeting 2004; IEEE, 2004 Dec 13 pp 889–892.
19. 10.1016/j.egypro.2015.07.08010.1016/j.egypro.2015.07.080 ↗
20. 10.1186/s11671-019-2969-z10.1186/s11671-019-2969-z ↗
21. 10.1063/1.9479410.1063/1.94794 ↗
22. 10.1080/1364281840824649410.1080/13642818408246494 ↗
23. 10.1109/ted.2009.203083310.1109/ted.2009.2030833 ↗
24. 10.1109/ted.2005.85969110.1109/ted.2005.859691 ↗
25. 10.1109/tnano.2004.82401610.1109/tnano.2004.824016 ↗
26. Rothschild, A.; Breuil, L.; Richard, O.; Conard, T.; Franquet, A.; Cacciato, A.; Debusschere, I.; Jurczak, M.; Van Houdt, J.; Kittl, J. A.; Ganguly, U. O2 Post Deposition Anneal of Al2O3 Blocking Dielectric for Higher Performance and Reliability of TANOS Flash Memory. 2009 Proceedings of the European Solid State Device Research Conference; IEEE, 2009 Sep 14 pp. 272–275.
27. 10.1063/1.175514110.1063/1.1755141 ↗
28. 10.1016/j.solmat.2015.06.00710.1016/j.solmat.2015.06.007 ↗
29. 10.1103/physrev.177.117910.1103/physrev.177.1179 ↗
30. 10.1016/j.mser.2014.11.00110.1016/j.mser.2014.11.001 ↗
31. 10.1039/c1nr10104h10.1039/c1nr10104h ↗
32. Jang, J.; Kim, H. S.; Cho, W.; Cho, H.; Kim, J.; Shim, S. I.; Jeong, J. H.; Son, B. K.; Kim, D. W.; Shim, J. J.; Lim, J. S. Vertical Cell Array Using TCAT (Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory. 2009 Symposium on VLSI; IEEE, 2009 Jun 16 pp 192–193.
33. 10.1063/1.278602110.1063/1.2786021 ↗
34. 10.1016/j.tsf.2004.05.03110.1016/j.tsf.2004.05.031 ↗
35. 10.1002/smll.20190572610.1002/smll.201905726 ↗
36. 10.1002/adma.20200169910.1002/adma.202001699 ↗
37. 10.1063/1.502141110.1063/1.5021411 ↗
38. 10.1063/1.344250210.1063/1.3442502 ↗
39. 10.1063/1.344683510.1063/1.3446835 ↗