journal article·2022-02-09

A Polarization-Switching, Charge-Trapping, Modulated Arithmetic Logic Unit for In-Memory Computing Based on Ferroelectric Fin Field-Effect Transistors

Zhaohao Zhang, Yanna Luo, Yan Cui, Hong Yang, Qingzhu Zhang, Gaobo Xu, Zhenhua Wu, Jinjuan Xiang, Qianqian Liu, Huaxiang Yin, Shujuan Mao, Xiaolei Wang, Junjie Li, Yongkui Zhang, Qing Luo, Jianfeng Gao, Wenjuan Xiong, Jinbiao Liu, Yongliang Li, Junfeng Li, Jun Luo, Wenwu Wang

Publisher page

Abstract

Nonvolatile logic devices are crucial for the development of logic-in-memory (LiM) technology to build the next-generation non-von Neumann computing architecture. Ferroelectric field-effect transistors (Fe FET) are one of the most promising candidates for LiMs because of high compatibility with mainstream silicon-based complementary metal-oxide semiconductor processes, nonvolatile memory, and low power consumption. However, because of the unipolar characteristics of a Fe FET, a nonlinear XOR or XNOR logic gate function is difficult to realize with a single device. In addition, because single Fe polarization switch modulation is available in the devices, a reconfigurable logic gate usually needs multiple devices to construct and realize fewer logic functions. Here, we introduced polarization-switching (PS) and charge-trapping (CT) effects in a single Fe FET and fabricated a multi-field-effect transistor with bipolar-like characteristics based on advanced 10 nm node fin field-effect transistors (PS-CT FinFET) with 9 nm thick Hf0.5Zr0.5O2 films. The special hybrid effects of charge-trapping and polarization-switching enabled eight Boolean logic functions with a single PS-CT FinFET and 16 Boolean logic functions with two complementary PS-CT FinFETs were obtained with three operations. Furthermore, reconfigurable full 1 bit adder and subtractor functions were demonstrated by connecting only two n-type and two p-type PS-CT FinFET devices, indicating that the technology was promising for LiM applications.
Source: openalex_inverted_index · Quality: baseline

Research context

OpenAlex topics: Advanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · Semiconductor materials and devices

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

Affiliations

Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), Beijing 100029, China

The University of Chinese Academy of Sciences, Beijing 100049, China

Funding

Beijing Municipal Science and Technology Commission · Youth Innovation Promotion Association of the Chinese Academy of Sciences · National Natural Science Foundation of China

References (30)

Show source-provided references
1. 10.1145/1941487.194150710.1145/1941487.1941507 ↗
2. 10.1038/nnano.2012.24010.1038/nnano.2012.240 ↗
3. 10.1038/nnano.2015.2910.1038/nnano.2015.29 ↗
4. 10.1002/adfm.20190566010.1002/adfm.201905660 ↗
5. 10.1038/nature0894010.1038/nature08940 ↗
6. Ding Z. D. · 2011
7. 10.1088/0957-4484/23/30/30520510.1088/0957-4484/23/30/305205 ↗
8. 10.1063/1.492234410.1063/1.4922344 ↗
9. 10.1021/acsami.6b1146510.1021/acsami.6b11465 ↗
10. 10.1021/nn101516t10.1021/nn101516t ↗
11. 10.1002/adfm.20150086510.1002/adfm.201500865 ↗
12. 10.1109/TED.2020.304654110.1109/TED.2020.3046541 ↗
13. 10.1145/1596543.159654810.1145/1596543.1596548 ↗
14. 10.1109/TMAG.2014.232977410.1109/TMAG.2014.2329774 ↗
15. Böscke, T. S.; Müller, J.; Bräuhaus, D.; Schröder, U.; Böttger, U. Ferroelectricity in Hafnium Oxide: CMOS Compatible Ferroelectric Field Effect Transistors. in 2011 International electron devices meeting; IEEE: Washington, DC, USA, 2011, pp 24.5.1–24.5.4.10.1109/IEDM.2011.6131606 ↗
16. 10.1109/TED.2013.228346510.1109/TED.2013.2283465 ↗
17. 10.1021/nl071804g10.1021/nl071804g ↗
18. Chiu, Y. C.; Cheng, C. H.; Chang, C. Y.; Lee, M. H.; Hsu, H. H.; Yen, S. S. Low Power 1T DRAM/NVM Versatile Memory Featuring Steep Sub-60-mV/decade Pperation, Fast 20-ns Speed, and Robust 85°C-extrapolated 1016 endurance, in: Symposium on VLSI Technology; IEEE: Kyoto, Japan, 2015, pp. T184–T185.10.1109/VLSIT.2015.7223671 ↗
19. Beyer, S.; Trentzsch, M.; Flachowsky, S.; Richter, R.; Rice, B. A 28nm HKMG Super Low Power Embedded NVM Technology Based on Ferroelectric FETs. in IEDM Tech. Dig.; IEEE: Washington, DC, USA, .2016, pp 11.5.1–11.5.4.10.1109/IEDM.2016.7838397 ↗
20. 10.1038/s41928-020-0433-910.1038/s41928-020-0433-9 ↗
21. Breyer T. · 2014
22. Yin, X. Z.; Aziz, A.; Nahas, J.; Datta, S.; Gupta, S.; Niemier, M.; Hu, X S. Exploiting Ferroelectric FETs for Low-power Nonvolatile Logic-inmemory Circuits, In IEEE/ACM International Conference on Computer-Aided Design; IEEE: Austin, TX, USA, 2016, pp 1–8.10.1145/2966986.2967037 ↗
23. 10.1080/10584587.2012.66083610.1080/10584587.2012.660836 ↗
24. Breyer, E.T.; Mulaosmanovic, H.; Mikolajick, T.; Slesazeck, S. Reconfigurable NAND/NOR Logic Gates in 28 nm HKMG and 22 nm FD-SOI FeFET Technology. in IEDM Tech. Dig.; IEEE: Washington, DC, USA, 2017; pp 28.5.1–4.10.1109/IEDM.2017.8268471 ↗
25. 10.1109/LED.2019.289136410.1109/LED.2019.2891364 ↗
26. Luo, Q.; Gong, T.; Cheng, Y.; Zhang, Q.; Yu, H.; Yu, J.; Ma, H.; Xu, X.; Huang, K.; Zhu, X.; Dong, D.; Yin, J.; Yuan, P.; Tai, L.; Gao, J.; Li, J.; Yin, H.; Long, S.; Liu, Q.; Lv, H.; Liu, M. Hybrid 1 T e-DRAM.; e-NVM Realized in One 10 nm node Ferro FinFET device with Charge Trapping and Domain Switching Effects. in IEDM Tech. Dig.; IEEE: Washington, DC, USA, 2018.10.1109/IEDM.2018.8614650 ↗
27. Xiang Y. · 2020
28. 10.1109/LED.2021.307443410.1109/LED.2021.3074434 ↗
29. Toprasertpong K. · 2019
30. 10.1038/s41928-021-00591-z10.1038/s41928-021-00591-z ↗