Pristine Graphene Insertion at the Metal/Semiconductor Interface to Minimize Metal-Induced Gap States

Metal (M) contact with a semiconductor (S) introduces metal-induced gap states (MIGS), which makes it difficult to study the intrinsic electrical properties of S. A bilayer of metal with graphene (Gr), i.e., a M/Gr bilayer, may form a contact with S to minimize MIGS. However, it has been challenging to realize the pristine M/Gr/S junctions without interfacial contaminants, which result in additional interfacial states. Here, we successfully demonstrate the atomically clean M/Gr/n-type silicon (Si) junctions via all-dry transfer of M/Gr bilayers onto Si. The fabricated M/Gr/Si junctions significantly increase the current density J at reverse bias, compared to those of M/Si junctions without a Gr interlayer (e.g., by 105 times for M = Au in Si(111)). The increase of the reverse J by a Gr interlayer is more prominent in Si(111) than in Si(100), whereas in M/Si junctions, J is independent of the type of Si surface. The different transport data between M/Gr/Si(111) and M/Gr/Si(100) are consistent with Fermi-level pinning by different surface states of Si(111) and Si(100). Our findings suggest the effective way to suppress MIGS by an introduction of the clean Gr interlayer, which paves the way to study intrinsic electrical properties of various materials.