Defect Engineering in Thickness-Controlled Bi₂O₂Se-Based Transistors by Argon Plasma Treatment

We present a simple, effective, and controllable method to uniformly thin down the thickness of as-exfoliated two-dimensional Bi2O2Se nanoflakes using Ar+ plasma treatment. Atomic force microscopy (AFM) images and Raman spectra indicate that the surface morphology and crystalline quality of etched Bi2O2Se nanoflakes remain almost unaffected. X-ray photoelectron spectra (XPS) indicate that the O and Se vacancies created during Ar+ plasma etching on the top surface of Bi2O2Se nanoflakes are passivated by forming an ultrathin oxide layer with UV O3 treatment. Moreover, a bottom-gate Bi2O2Se-based field-effect transistor (FET) was constructed to research the effect of thicknesses and defects on electronic properties. The on-current/off-current (Ion/Ioff) ratio of the Bi2O2Se FET increases with decreasing Bi2O2Se thickness and is further improved by UV O3 treatment. Eventually, the thickness-controlled Bi2O2Se FET achieves a high Ion/Ioff ratio of 6.0 × 104 and a high field-effect mobility of 5.7 cm2 V–1 s–1. Specifically, the variation trend of the Ion/Ioff ratio and the electronic transport properties for the bottom-gate Bi2O2Se-based FET are well described by a parallel resistor model (including bulk, channel, and defect resistance). Furthermore, the Ids–Vgs hysteresis and its inversion with UV irradiation were observed. The pulsed gate and drain voltage measurements were used to extract trap time constants and analyze the formation mechanism of different hysteresis. Before UV irradiation, the origin of clockwise hysteresis is attributed to the charge trapping/detrapping of defects at the Bi2O2Se/SiO2 interface and in the Bi2O2Se bulk. After UV irradiation, the large anticlockwise hysteresis is mainly due to the tunneling between deep-level oxygen defects in SiO2 and p++-Si gate, which implies the potential in nonvolatile memory.