Engineering Top Gate Stack for Wafer-Scale Integrated Circuit Fabrication Based on Two-Dimensional Semiconductors

In recent years, two-dimensional (2D) semiconductors have attracted considerable attention from both academic and industrial communities. Recent research has begun transforming from constructing basic field-effect transistors (FETs) into designing functional circuits. However, device processing remains a bottleneck in circuit-level integration. In this work, a non-destructive doping strategy is proposed to modulate precisely the threshold voltage (VTH) of MoS2-FETs in a wafer scale. By inserting an Al interlayer with a varied thickness between the high-k dielectric and the Au top gate (TG), the doping could be controlled. The full oxidation of the Al interlayer generates a surplus of oxygen vacancy (Vo) in the high-k dielectric layer, which further leads to stable electron doping. The proposed strategy is then used to optimize an inverter circuit by matching the electrical properties of the load and driver transistors. Furthermore, the doping strategy is used to fabricate digital logic blocks with desired logic functions, which indicates its potential to fabricate fully integrated multistage logic circuits based on wafer-scale 2D semiconductors.