Show source-provided references
3. Mertens, H.; Ritzenthaler, R.; Hikavyy, A.; Kim, M.S.; Tao, Z.; Wostyn, K.; Chew, S. A.; De Keersgieter, A.; Mannaert, G.; Rosseel, E. Gate-All-Around MOSFETs Based on Vertically Stacked Horizontal Si Nanowires in a Replacement Metal Gate Process on Bulk Si Substrates. In 2016 IEEE Symposium on VLSI Technology; IEEE: 2016; pp 1–2.
10.1109/VLSIT.2016.7573416 ↗4. Veloso, A.; Huynh-Bao, T.; Rosseel, E.; Paraschiv, V.; Devriendt, K.; Vecchio, E.; Delvaux, C.; Chan, B.; Ercken, M.; Tao, Z. Challenges and Opportunities of Vertical FET Devices Using 3D Circuit Design Layouts. In 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S); IEEE: 2016; pp 1–3.
10.1109/S3S.2016.7804409 ↗7. Choi, Y.K.; Lindert, N.; Xuan, P.; Tang, S.; Ha, D.; Anderson, E.; King, T.J.; Bokor, J.; Hu, C. Sub-20 nm CMOS FinFET Technologies. In International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224; IEEE: 2001; pp 19.1.1–19.1.4.
8. Ghani, T.; Armstrong, M.; Auth, C.; Bost, M.; Charvat, P.; Glass, G.; Hoffmann, T.; Johnson, K.; Kenyon, C.; Klaus, J. A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors. In IEEE International Electron Devices Meeting 2003; IEEE: 2003; pp 11.6.1–11.6.3.
10. Rim, K.; Welser, J.; Hoyt, J.; Gibbons, J. Enhanced Hole Mobilities in Surface-Channel Strained-Si P-MOSFETs. In Proceedings of International Electron Devices Meeting; IEEE: 1995; pp 517–520.
14. Thean, A. V.; Yakimets, D.; Bao, T. H.; Schuddinck, P.; Sakhare, S.; Bardon, M. G.; Sibaja-Hernandez, A.; Ciofi, I.; Eneman, G.; Veloso, A. Vertical Device Architecture for 5nm and Beyond: Device & Circuit Implications. In 2015 Symposium on VLSI Technology (VLSI Technology); IEEE: 2015; pp T26–T27.
10.1109/VLSIT.2015.7223689 ↗16. Shul R. J. · 2011
38. Guder M. · 2008 · 79
40. Zhao X.-b. · Chin. J. Process Eng. · 2008 · 8 · 35
49. Kim T. G. · 2012 · 123