journal article·2019-10-09Open access

Selective Wet Etching of Silicon Germanium in Composite Vertical Nanowires

Zhaslan Baraissov, Antoine Pacco, Siddardha Koneti, Geeta Bisht, Federico Panciera, Frank Holsteyns, Utkur Mirsaidov

ACS Applied Materials & Interfaces· Volume 11· Issue 40

Abstract

Silicon germanium (SixGe1–x or SiGe) is an important semiconductor material for the fabrication of nanowire-based gate-all-around transistors in the next-generation logic and memory devices. During the fabrication process, SiGe can be used either as a sacrificial layer to form suspended horizontal Si nanowires or, because of its higher carrier mobility, as a possible channel material that replaces Si in both horizontal and vertical nanowires. In both cases, there is a pressing need to understand and develop nanoscale etching processes that enable controlled and selective removal of SiGe with respect to Si. Here, we developed and tested solution-based selective etching processes for SiGe in composite (SiNx/Si0.75Ge0.25/Si) vertical nanowires. The etching solutions were formed by mixing acetic acid (CH3COOH), hydrogen peroxide (H2O2), and hydrofluoric acid (HF). Here, CH3COOH and H2O2 react to form highly oxidizing peracetic acid (PAA or CH3 CO3H). The hydrofluoric acid serves both as a catalyst for PAA formation and as an etchant for oxidized SiGe. Our study shows that an increase in any of the two oxidizer (H2O2 and PAA) concentrations increases the etch rate, and the fastest etch rate of SiGe is associated with the highest PAA concentration. Moreover, using in situ liquid-phase TEM imaging, we tested the stability of nanowires during wet etching and identified the SiGe/Si interface to be the weakest plane; we found that once the diameter of the 160-nm-tall Si0.75Ge0.25 nanowire reaches ∼15 nm during the etching, the nanowire breaks at or very close to this interface. Our study provides important insight into the details of the nanoscale wet etching of SiGe and some of the associated failure modes that are becoming extremely relevant for the fabrication processes as the size of the transistors shrink with every new device generation.
Source: openalex_inverted_index · Quality: baseline

Research context

OpenAlex topics: Advancements in Semiconductor Devices and Circuit Design · Nanowire Synthesis and Applications · Semiconductor materials and devices

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

Affiliations

Department of Physics, National University of Singapore, Singapore 117551, Singapore

Centre for BioImaging Sciences, Department of Biological Sciences, National University of Singapore, Singapore 117557, Singapore

imec, Kapeldreef 75, Leuven B-3001, Belgium

Centre for Advanced 2D Materials and Graphene Research Centre, National University of Singapore, Singapore 117546, Singapore

Department of Materials Science and Engineering, National University of Singapore, Singapore 117575, Singapore

Funding

National Research Foundation Singapore

References (52)

Show source-provided references
1. 10.1038/530144a10.1038/530144a ↗
2. 10.1109/TED.2012.219312910.1109/TED.2012.2193129 ↗
3. Mertens, H.; Ritzenthaler, R.; Hikavyy, A.; Kim, M.S.; Tao, Z.; Wostyn, K.; Chew, S. A.; De Keersgieter, A.; Mannaert, G.; Rosseel, E. Gate-All-Around MOSFETs Based on Vertically Stacked Horizontal Si Nanowires in a Replacement Metal Gate Process on Bulk Si Substrates. In 2016 IEEE Symposium on VLSI Technology; IEEE: 2016; pp 1–2.10.1109/VLSIT.2016.7573416 ↗
4. Veloso, A.; Huynh-Bao, T.; Rosseel, E.; Paraschiv, V.; Devriendt, K.; Vecchio, E.; Delvaux, C.; Chan, B.; Ercken, M.; Tao, Z. Challenges and Opportunities of Vertical FET Devices Using 3D Circuit Design Layouts. In 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S); IEEE: 2016; pp 1–3.10.1109/S3S.2016.7804409 ↗
5. 10.1109/TED.2015.241492410.1109/TED.2015.2414924 ↗
6. 10.1088/0034-4885/65/1/20210.1088/0034-4885/65/1/202 ↗
7. Choi, Y.K.; Lindert, N.; Xuan, P.; Tang, S.; Ha, D.; Anderson, E.; King, T.J.; Bokor, J.; Hu, C. Sub-20 nm CMOS FinFET Technologies. In International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224; IEEE: 2001; pp 19.1.1–19.1.4.
8. Ghani, T.; Armstrong, M.; Auth, C.; Bost, M.; Charvat, P.; Glass, G.; Hoffmann, T.; Johnson, K.; Kenyon, C.; Klaus, J. A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors. In IEEE International Electron Devices Meeting 2003; IEEE: 2003; pp 11.6.1–11.6.3.
9. 10.1063/1.273056110.1063/1.2730561 ↗
10. Rim, K.; Welser, J.; Hoyt, J.; Gibbons, J. Enhanced Hole Mobilities in Surface-Channel Strained-Si P-MOSFETs. In Proceedings of International Electron Devices Meeting; IEEE: 1995; pp 517–520.
11. 10.1063/1.181997610.1063/1.1819976 ↗
12. 10.1149/07204.0031ecst10.1149/07204.0031ecst ↗
13. 10.1063/1.280258610.1063/1.2802586 ↗
14. Thean, A. V.; Yakimets, D.; Bao, T. H.; Schuddinck, P.; Sakhare, S.; Bardon, M. G.; Sibaja-Hernandez, A.; Ciofi, I.; Eneman, G.; Veloso, A. Vertical Device Architecture for 5nm and Beyond: Device & Circuit Implications. In 2015 Symposium on VLSI Technology (VLSI Technology); IEEE: 2015; pp T26–T27.10.1109/VLSIT.2015.7223689 ↗
15. 10.1186/s11671-016-1396-710.1186/s11671-016-1396-7 ↗
16. Shul R. J. · 2011
17. 10.1016/j.mee.2006.10.05810.1016/j.mee.2006.10.058 ↗
18. 10.1149/1.220957010.1149/1.2209570 ↗
19. 10.1063/1.347465210.1063/1.3474652 ↗
20. 10.1063/1.35118310.1063/1.351183 ↗
21. 10.1116/1.239324410.1116/1.2393244 ↗
22. 10.1116/1.57735910.1116/1.577359 ↗
23. 10.1016/j.mser.2004.11.00210.1016/j.mser.2004.11.002 ↗
24. 10.1063/1.10506710.1063/1.105067 ↗
25. 10.1149/1.206901210.1149/1.2069012 ↗
26. 10.1149/1.242608210.1149/1.2426082 ↗
27. 10.1149/1.242532110.1149/1.2425321 ↗
28. 10.1149/1.242761710.1149/1.2427617 ↗
29. 10.1149/1.208553910.1149/1.2085539 ↗
30. 10.1080/10643389.2016.127234310.1080/10643389.2016.1272343 ↗
31. 10.1016/j.molcata.2007.03.01210.1016/j.molcata.2007.03.012 ↗
32. 10.1021/ja01620a02310.1021/ja01620a023 ↗
33. 10.1021/ja993803z10.1021/ja993803z ↗
34. 10.1016/S0169-4332(97)00511-410.1016/S0169-4332(97)00511-4 ↗
35. 10.1149/1.338294410.1149/1.3382944 ↗
36. 10.1149/1.204416110.1149/1.2044161 ↗
37. 10.1016/j.sse.2004.01.01210.1016/j.sse.2004.01.012 ↗
38. Guder M. · 2008 · 79
39. 10.1149/1.298680110.1149/1.2986801 ↗
40. Zhao X.-b. · Chin. J. Process Eng. · 2008 · 8 · 35
41. 10.1007/s11176-005-0378-810.1007/s11176-005-0378-8 ↗
42. 10.1007/s11746-005-1070-910.1007/s11746-005-1070-9 ↗
43. 10.1039/C4SM01520G10.1039/C4SM01520G ↗
44. 10.1149/2.010401jss10.1149/2.010401jss ↗
45. 10.1088/0957-4484/25/3/03530210.1088/0957-4484/25/3/035302 ↗
46. 10.1021/acs.nanolett.7b0019610.1021/acs.nanolett.7b00196 ↗
47. 10.1038/nnano.2011.16110.1038/nnano.2011.161 ↗
48. 10.1088/0268-1242/23/8/08502110.1088/0268-1242/23/8/085021 ↗
49. Kim T. G. · 2012 · 123
50. 10.3390/cryst806025710.3390/cryst8060257 ↗
51. 10.1039/C4NR04315D10.1039/C4NR04315D ↗
52. 10.1149/1.363084310.1149/1.3630843 ↗