Thermally Activated Defect Engineering for Highly Stable and Uniform ALD-Amorphous IGZO TFTs with High-Temperature Compatibility

Highly stable IGZO thin-film transistors derived from atomic layer deposition are crucial for the semiconductor industry. However, unavoidable defect generation during high-temperature annealing results in abnormal positive bias temperature stress (PBTS). Herein, we propose a defect engineering method by controlling the gate insulator (GI) deposition temperature. Applying a GI deposition temperature of 400 °C to the In 0.52 Ga 0.18 Zn 0.30 O active layer effectively suppresses defects even after 600 °C annealing, preserving the amorphous phase of IGZO. The device exhibits a threshold voltage ( V TH ) of 0.05 V, a field-effect mobility of 27.6 cm 2 /Vs, a subthreshold swing of 61 mV/decade, and a hysteresis voltage of 0.01 V, demonstrating highly reliable PBTS and negative bias temperature stress. A power-law fit of the PBTS stability under 2 MV/cm of gate field stress and 120 °C of temperature stress predicts a V TH shift of −0.01 V after 10 years. Moreover, the proposed method ensures reliable uniformity over a large 4 in. area.