Selective Electroless Metallization of Patterned Polymeric Films for Lithography Applications

The fabrication of electrical interconnects to provide power for and communication with computers as their component complementary metal oxide semiconductor (CMOS) devices continue to shrink in size presents significant materials and processing compatibility challenges. We describe here our efforts to address these challenges using top-surface imaging and hybrid photoresist/self-assembled monolayer patterning approaches, in conjunction with selective electroless metal deposition, to develop processes capable of fabricating appropriate submicron and nanoscale metal features useful as electrical interconnects, as well as plasma-etch-resistant masks and metal diffusion barriers. Our efforts focus on the development of cost-effective methods compatible with a manufacturing environment that satisfy materials and process constraints associated with CMOS device production. We demonstrate the fabrication of approximately 50-nm-width features in metal with high fidelity and sufficient control of edge acuity to satisfy current industry design rules using our processes and discuss the challenges and opportunities for fabrication of analogous sub-10-nm metal features.