Low-power double-gate MoS₂ negative capacitance transistors with near-zero DIBL

Abstract Negative capacitance (NC) devices hold great promise for improving subthreshold slope (SS). However, the theoretical exploration of the short-channel effect in NC and two-dimensional (2D) materials remains an ongoing challenge in device scaling. The present work demonstrates a double-gate MoS₂ negative capacitance field-effect transistor (MoS₂ DG-NCFET) with low power and near-zero drain-induced barrier lowering (DIBL) by exploring its design space considering the impact of various MoS₂ layers, with the aid of the developed 2D short-channel model containing the NC effect and numerical simulation. The proposed monolayer MoS₂ DG-NCFET model is solved by unifying the long and short channel models coupled with the one-dimensional Landau-Khalatnikov equation. The study indicates that a lower SS, considerable voltage saving ({V}_saving), and even the ability to achieve zero DIBL are seen in monolayer MoS₂ devices when compared with those of non-2D MoS₂, due to the combination of the atomic-scale thickness of channels and the double-gate structure. This study provides an insight for further reducing the feature size of ultralow power transistors.