journal article·2022-11-01

Role of temperature on linearity and analog/RF performance merits of a negative capacitance FinFET

Rajeewa Kumar Jaisawal, Sunil Rathore, Navneet Gandhi, Pravin N Kondekar, Navjeet Bagga

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Abstract

Abstract Temperature plays a decisive role in semiconductor device performance and reliability analysis. The effect is more severe in a negative capacitance (NC) transistor, as the temperature modulates the ferroelectric polarization, implicitly included by the Landau coefficients (α, β, γ) in Technology Computer Aided Design (TCAD) simulations. In this paper, through TCAD simulations, the role of varying ambient temperature is investigated in the linearity and analog/radio-frequency (RF) merits of NC-FinFET. The varying temperature modulates the carrier mobility, the semiconductor bandgap, and the Landau parameter (α). We analyzed the analog/RF and linearity metrics, such as total gate capacitance (C gg), transconductance (g m), unity gain cut-off frequency (f T), the transconductance-frequency product, gain-bandwidth product, higher-order transconductance (g m2 and g m3), voltage intercept points, third-order power intercept and intermodulation points, and 1 dB CP using well-calibrated TCAD models. Our analysis reveals that these parameters are strongly dependent on temperature and the NC span (defined by using S-curve) shrinks with the rise in temperature. Finally, a source follower and three-stage ring oscillator are designed to test the frequency compatibility of the AC simulation for varying temperatures.
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Research context

OpenAlex topics: Ferroelectric and Negative Capacitance Devices · Semiconductor materials and devices · MXene and MAX Phase Materials

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References (26)

Show source-provided references
1. Reliability characterization of 10 nm FinFET technology with multi-VT gate stack for low power and high performance10.1109/IEDM.2016.7838420 ↗
2. Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques10.1088/1361-6641/ac6128 ↗
3. High performance 14 nm SOI FinFET CMOS technology with 0.0174 µm2 embedded DRAM and 15 levels of cumetallization10.1109/IEDM.2014.7046977 ↗
4. Investigation of ambient temperature and thermal contact resistance induced self-heating effects in nanosheet FET10.1088/1361-6641/ac62fb ↗
5. Use of negative capacitance to provide voltage amplification for low power nanoscale devices10.1021/nl071804g ↗
6. Cleaved-gate ferroelectric FET for reliable multi-level cell storage10.1109/IRPS48227.2022.9764553 ↗
7. Analysis and modeling of inner fringing field effect on negative capacitance FinFETs10.1109/TED.2019.2899810 ↗
8. BOX engineering to mitigate negative differential resistance in MFIS negative capacitance FDSOI FET: an analog perspective10.1088/1361-6528/ac328a ↗
9. Insights into the operation of negative capacitance FinFET for low power logic applications10.1016/j.mejo.2021.105321 ↗
10. Ferroelectricity in hafnium oxide thin films10.1063/1.3634052 ↗
11. Demonstration of high-speed hysteresis-free negative capacitance in ferroelectric Hf0.5Zr0.5O210.1109/IEDM.2018.8614677 ↗
12. Ferroelectricity in CMOS-compatible hafnium oxides: reviving the ferroelectric field-effect transistor technology10.1109/MNANO.2021.3098218 ↗
13. Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach10.1109/ESSDERC.2016.7599584 ↗
14. 14-nm FinFET technology for analog and RF applications10.1109/TED.2017.2776838 ↗
15. Intel 22 nm FinFET (22FFL) process technology for RF and mm wave applications and circuit design optimization for FinFET technology10.1109/IEDM.2018.8614490 ↗
16. User selection for millimeter wave non-uniform full dimensional MIMO10.1109/ACCESS.2020.3031466 ↗
17. Synopsys · 2020
18. An improved electron and hole mobility model for general purpose device simulation10.1109/16.622611 ↗
19. Engineering negative differential resistance in ncfets for analog applications10.1109/TED.2018.2817238 ↗
20. Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques10.1109/16544417 ↗
21. Impact of temperature variations on the device and circuit performance of tunnel fet: a simulation study10.1109/TNANO.2013.2276401 ↗
22. Performance enhancement of novel InAs/Si hetero double-gate tunnel FET using Gaussian doping10.1109/TED.2015.2503141 ↗
23. Design optimization of three-stacked nanosheet FET from self-heating effects perspective10.1109/TDMR.2022.3181672 ↗
24. Interfacial charge analysis of heterogeneous gate dielectric-gate all around-tunnel FET for improved device reliability10.1109/TDMR2016.2564448 ↗
25. An investigation of linearity performance and intermodulation distortion of GME CGT MOSFET for RFIC design10.1109/TED.2012.2219537 ↗
26. A new aspect of saturation phenomenon in FinFETs and its implication on analog circuits10.1109/TED.2019.2914867 ↗