A Drain Current and Transconductance Analytical Model for Symmetric Double Gate Junctionless FENT
Source abstract
Abstract
This paper presents an analytical model of various electrical parameters for an ultra thin symmetric double gate (SDG) junctionless field effect nanowire transistor (JLFENT). The model works for all the regions of operation of the nanowire transistor without using any fitting parameter. The surface potential is derived based on the solutions of Poisson’s and current continuity equations by using appropriate boundary conditions. The Pao–Sah double integral was used to obtain the drain current, transconductance and drain conductance. The results obtained from analytical model are validated by comparing with GENIUS 3D TCAD simulations. The simplicity of the model makes it appropriate to be a SPICE compatible model.
Source: crossref · Quality: baseline
Research context
OpenAlex topics: Advancements in Semiconductor Devices and Circuit Design · Semiconductor materials and devices · Nanowire Synthesis and Applications
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
North Eastern Hill University (A Central University of India)
References (20)
Show source-provided references
1. J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, Blake, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, Nanowire transistors without junctions,, Nat. Nanotechnol., vol. 5, no. 3, p.225–229, (2010).10.1038/nnano.2010.15 ↗
2. H. C. Lin, C. I. Lin, and T. Y. Huang, Characteristics of n-Type junctionless poly-Si thin-film transistors with an ultrathin channel,, IEEE Electron Device Lett., vol. 33, no. 1, p.53–55, (2012).10.1109/led.2011.2171914 ↗
3. C. W. Lee, A. N. Nazarov, I. Ferain, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, R. T. Doria, and J. P. Colinge, Low subthreshold slope in junctionless multigate transistors,, Appl. Phys. Lett., vol. 96, no. 10, p.10–12, (2010).10.1063/1.3358131 ↗
4. C. J. Su, T. I. Tsai, Y. L. Liou, Z. M. Lin, H. C. Lin, and T. S. Chao, Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels,, IEEE Electron Device Lett., vol. 32, no. 4, p.521–523, (2011).10.1109/led.2011.2107498 ↗
5. A. Kranti, R. Yan, C. W. Lee, I. Ferain, R. Yu, N. D. Akhavan, P. Razavi, and J. P. Colinge, Junctionless nanowire transistor (JNT): Properties and design guidelines,, in 2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010, (2010).10.1109/essderc.2010.5618216 ↗
6. J. T. Park, J. Y. Kim, C. W. Lee, and J. P. Colinge, Low-temperature conductance oscillations in junctionless nanowire transistors,, Appl. Phys. Lett., vol. 97, no. 17, (2010).10.1063/1.3506899 ↗
7. M. M. Shulaker, G. Hills, N. Patil, H. Wei, H. Y. Chen, H. S. P. Wong, and S. Mitra, Carbon nanotube computer,, Nature, vol. 501, no. 7468, p.526–530, (2013).10.1038/nature12502 ↗
8. R. Marani and A. G. Perri, A Design Technique of CNTFET-Based Ternary Logic Gates in Verilog-A,, ECS J. Solid State Sci. Technol., (2019).10.1149/2.0181904jss ↗
9. H. S. P. Wong, Beyond the conventional transistor,, Solid. State. Electron., vol. 49, no. 5, p.755–762, (2005).10.1016/j.sse.2004.10.014 ↗
10. R. Maurand, X. Jehl, D. Kotekar-Patil, A. Corna, H. Bohuslavskyi, R. Laviéville, L. Hutin, S. Barraud, M. Vinet, M. Sanquer, and S. De Franceschi, A CMOS silicon spin qubit,, Nat. Commun., vol. 7, no. 13575, (2016).10.1038/ncomms13575 ↗
11. Z. Chen, Y. Xiao, M. Tang, Y. Xiong, J. Huang, J. Li, X. Gu, and Y. Zhou, Surface-potential-based drain current model for long-channel junctionless double-gate MOSFETs,, IEEE Trans. Electron Devices, vol. 59, no. 12, p.3292–3298, (2012).10.1109/ted.2012.2221164 ↗
12. J. P. Duarte, S. J. Choi, and Y. K. Choi, A full-range drain current model for double-gate junctionless transistors,, IEEE Trans. Electron Devices, vol. 58, no. 12, p.4219–4225, (2011).10.1109/ted.2011.2169266 ↗
13. J. M. Sallese, N. Chevillon, C. Lallement, B. Iñiguez, and F. Prégaldiny, Charge-based modeling of junctionless double-gate field-effect transistors,, IEEE Trans. Electron Devices, vol. 58, no. 8, p.2628–2637, (2011).10.1109/ted.2011.2156413 ↗
14. E. Gnani, A. Gnudi, S. Reggiani, and G. Baccarani, Theory of the junctionless nanowire FET,, IEEE Trans. Electron Devices, vol. 58, no. 9, p.2903–2910, (2011).10.1109/ted.2011.2159608 ↗
15. H. C. Pao and C. T. Sah, Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors,, Solid State Electron., vol. 9, p.927–937, (1966).10.1016/0038-1101(66)90068-2 ↗
16. B. Yu, L. Wang, Y. Yuan, P. M. Asbeck, and Y. Taur, Scaling of nanowire transistors,, IEEE Trans. Electron Devices, vol. 55, no. 11, p.2846–2858, (2008).10.1109/ted.2008.2005163 ↗
17. N. Bora and R. Subadar, A Complete Analytical Model of Surface Potential and Drain Current for an Ultra Short Channel Double Gate Asymmetric Junctionless Transistor,, J. Nanoelectron. Optoelectron., vol. 14, no. 9, p.1283–1289, Jul. (2019).10.1166/jno.2019.2643 ↗
18. H. Lu, S. Member, and Y. Taur, An Analytic Potential Model for Symmetric and Asymmetric DG MOSFETs,, IEEE Trans. Electron Devices, vol. 53, no. 5, p.1161–1168, (2006).10.1109/ted.2006.872093 ↗
19. R. K. Baruah and N. Bora, Analytic solution for symmetric DG MOSFETs with gate-oxide-thickness asymmetry,, J. Comput. Theor. Nanosci., vol. 8, no. 10, p.2025–2028, (2011).10.1166/jctn.2011.1920 ↗
20. Cogenda Pte Ltd., Genius, 3-D Device Simulator, Reference Manual., 1.9.3. Singapore, (2014).