Hysteresis characteristics in low temperature poly‐Si thin film transistors

Abstract The dependence of hysteresis characteristics in low temperature poly‐Si (LTPS) thin film transistors (TFTs) on the gatesource voltage (Vgs) or the drain‐source voltage (Vds) bias is investigated and discussed. The hysteresis levels in both p‐type and n‐type LTPS TFTs are independent of Vds bias but increase as the sweep range of Vgs increases. It has been found that the hysteresis in both p‐type and n‐type LTPS TFTs originated from charge trapping and de‐trapping in the channel region rather than at the source/drain edges.