Gate driver-in-panel circuit using low-temperature polycrystalline silicon and oxide TFTs with mitigated positive bias temperature stress

This study featured a driving circuit focused on enhancing the reliability of the gate driver-in-panel (GIP) circuit, exhibiting stable performance while leveraging the low off-current characteristics of oxide thin-film transistors (TFTs). Through the proposed design strategy, compared with existing GIP circuits, a seven-transistor-based GIP circuit was successfully implemented using only six transistors, achieving a power consumption saving of approximately 5% to 10%. Additionally, the circuit demonstrated a large threshold voltage (VTH) shift margin for the oxide TFTs, ranging from −15 V to +15 V. Furthermore, when the output voltage was high, the circuit showed vulnerability from a positive bias temperature stress (PBTS) perspective, as the VTH variation of the oxide TFT was relatively larger than that of the LTPS TFT. This vulnerability can be improved by connecting the source to the bottom gate.The proposed circuit’s performance was validated through simulation and display panel fabrication, which has led to the development of a new proposed GIP circuit, demonstrating not only stable driving characteristics but also great potential for reduced power consumption. This design strategy is expected to be beneficial to researchers and electrical engineers.