New dynamic logic gate design method for improved TFT circuit performance

Abstract We explored a new way of designing dynamic logic gates with low temperature polysilicon thin film transistors to increase the speed. The proposed architecture of logic gates utilizes the structural advantage of smaller junction capacitance of thin film transistors. This method effectively blocks leakage of current through the thin film transistors. Furthermore, the number of transistors used in logic gates is reduced thereby reducing power consumption and chip area. Through HSPICE simulation, it is confirmed that the circuit speed is also improved in all logic gates designed.