High-Efficiency, Low-Power, Fully Integrated Neural Electrical Stimulation Circuit

This paper presents a highly efficient, low-power, fully integrated neural stimulation circuit implemented using solely low-voltage devices. The circuit primarily consists of a high-voltage-generation circuit, an output driver circuit, and a constant-current source, designed and simulated using a 180 nm low-voltage CMOS process. The high-voltage-generation circuit utilizes a negative-voltage-generation module together with a series–parallel capacitor charge pump circuit, which effectively reduces the number of charge pump stages by three, and saves 29% of the area compared to a conventional charge pump circuit. A bootstrap clock generation circuit was utilized to generate the control signal to ensure that all transistors work within their voltage limit. To realize the high-voltage output driver circuit using low-voltage devices, a stacked transistor structure with deep N-well (DNW) devices was utilized. The four different output voltage levels from the high-voltage-generation circuit were utilized to generate a different voltage domain of control signals and bias voltage for the stacked transistors, making sure that all transistors work within their voltage limit. Simulation results show that the high-voltage-generation circuit can generate an output of up to 12.69 V from a 1.65 V low input voltage, with a maximum output current of 1 mA, achieving 74.9% efficiency. The overall efficiency of the neural stimulation circuit, including the high-voltage-generation circuit, output driver circuit and constant-current source, reaches 74% under the voltage-controlled stimulation (VCS) mode and 59.5% under the current-controlled stimulation (CCS) mode, whereas the standby static power consumption is as low as 66 pW.