Self-delamination based double-sided MOSFET fabrication on single crystalline ultrathin silicon

Abstract Ultrathin silicon (UTSi) has emerged as a promising platform for next-generation flexible and high-density electronic systems, owing to its mechanical flexibility, excellent surface quality, and compatibility with standard semiconductor processes. While double-sided device fabrication on UTSi evidently provides enhanced areal device density or multifunctionality for UTSi, fabrication challenges remain due to the fragility of the UTSi and process complexity. Here, we present the fabrication and characterization of double-sided metal-oxide-semiconductor field-effect transistor (MOSFET) arrays on a 10 µm-thick freestanding UTSi derived from a silicon-on-insulator (SOI) wafer. Self-delamination-based processes were employed to enable sequential device integration on both front- and back-sides of UTSi without the use of adhesives or bonding layers. The UTSi demonstrated excellent structural integrity in terms of surface quality and stress concentration throughout 35 fabrication steps in total. Device-level examination confirmed that MOSFETs on both front- and back-sides of UTSi showed decent functional performance with threshold voltages of about 3 V and on/off current ratios of over 10⁴, respectively. Furthermore, MOSFETs on UTSi maintained stable device operation under mechanical bending, validating the excellent structural flexibility of UTSi without significantly compromising device capability. The front-side MOSFETs remained stable while a significant bias voltage was applied to the back-side gate exhibiting negligible change in transfer characteristics. Uniform threshold voltage and on/off current ratio across multiple devices confirmed excellent process consistency, while bending fatigue tests over 10 000 cycles demonstrated stable performance, highlighting the mechanical robustness of the UTSi for flexible and three-dimensional integration. This work establishes a mechanically robust and semiconductor process-compatible framework for double-sided device fabrication on UTSi, with potential for high-density 3D integration, flexible CMOS circuitry, and conformal electronics.