Effect of SrTiO3 thickness on the capacitance–voltage characteristics of (La,Sr)CoO3/(Pb,La)(Zr,Ti)O3/SrTiO3/LaVO3 epitaxial heterostructures

We report the effect of SrTiO3 thickness on the capacitance–voltage (C–V) characteristics of (La,Sr)CoO3/(Pb,La)(Zr,Ti)O3/SrTiO3/LaVO3 metal–ferroelectric–insulator–semiconductor (MFIS) epitaxial heterostructures. The C–V measurement of the heterostructure exhibited the asymmetry of capacitance with respect to gate bias. Within the given thickness range (5–30 nm), the amount of capacitance reduction at positive gate bias and the rapidness of capacitance reduction decreased with increasing SrTiO3 thickness, which is consistent with the C–V characteristics of conventional silicon-based MFIS capacitors. These results suggest that quantitative understanding on the electrical behavior of oxide heterostructures is possible with C–V analysis, with potentially important implications on their device applications.