Reliability Enhancements in Memristive Neural Network Architectures
Source abstract
Abstract
Memristive Crossbar Arrays (MCAs) are widely used in designing fast and compact neuromorphic systems. However, such systems require on-chip implementation of the backpropagation algorithm to accommodate process variations. This paper proposes a low hardware overhead on-chip implementation of the backpropagation algorithm that utilizes effectively the very dense MCAs. On-chip learning using the proposed architecture increases the reliability of the neuromorphic system in the presence of process variations in the neural component. The second contribution of this paper is an architectural enhancement to cope with another reliability consideration, namely the aging transistors in the MCA. Experimental results show the impact of reliability enhancement.
Source: openalex_inverted_index · Quality: baseline
Research context
OpenAlex topics: Advanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · Neuroscience and Neural Engineering
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
Department of Electrical and Computer Engineering, Southern Illinois University, Carbondale, IL, USA
Nvidia Corporation, Santa Clara, CA, USA
Funding
NSF I/UCRC for Embedded Systems at SIUC
References (47)
Show source-provided references
1. 10.1063/1.356488310.1063/1.3564883 ↗
2. 10.1109/EEEI.2012.637708110.1109/EEEI.2012.6377081 ↗
3. 10.1109/TVLSI.2011.210940410.1109/TVLSI.2011.2109404 ↗
4. 10.1145/3232195.323220810.1145/3232195.3232208 ↗
5. 10.1088/0957-4484/23/7/07520110.1088/0957-4484/23/7/075201 ↗
6. 10.1109/ASQED.2010.554831110.1109/ASQED.2010.5548311 ↗
7. 10.1109/TCSII.2015.243353610.1109/TCSII.2015.2433536 ↗
8. 10.1109/DFT.2009.2010.1109/DFT.2009.20 ↗
9. 10.1049/el.2012.229510.1049/el.2012.2295 ↗
10. Low power artificial neural network architecture
11. Training and operation of an integrated neuromorphic network based on metal-oxide memristors10.1038/nature14441 ↗
12. 10.1145/2628071.262808110.1145/2628071.2628081 ↗
13. 10.1063/1.504246810.1063/1.5042468 ↗
14. 10.1109/IJCNN.2015.728065810.1109/IJCNN.2015.7280658 ↗
15. 10.1109/ICRC.2017.812364210.1109/ICRC.2017.8123642 ↗
16. Minimal distributed bits in writing resistive crossbar memories
17. 10.1109/DFT.2018.860297610.1109/DFT.2018.8602976 ↗
18. 10.1109/TCAD.2016.260886310.1109/TCAD.2016.2608863 ↗
19. 10.1109/IRPS.2014.686115810.1109/IRPS.2014.6861158 ↗
20. 10.1109/NANOARCH.2015.718059010.1109/NANOARCH.2015.7180590 ↗
21. 10.1109/TETCI.2018.282991910.1109/TETCI.2018.2829919 ↗
22. 10.1109/VLSIT.1999.79934610.1109/VLSIT.1999.799346 ↗
23. 10.23919/DATE.2017.792699110.23919/DATE.2017.7926991 ↗
24. 10.1109/JSSC.2010.204012510.1109/JSSC.2010.2040125 ↗
25. 10.1145/2897937.289801110.1145/2897937.2898011 ↗
26. A survey of neuromorphic computing and neural networks in hardware
27. 10.1109/DDECS.2012.621908610.1109/DDECS.2012.6219086 ↗
28. Deep neural network using trainable activation functions
29. 10.1109/TCSI.2014.235971710.1109/TCSI.2014.2359717 ↗
30. 10.1109/JPROC.2011.216674910.1109/JPROC.2011.2166749 ↗
31. 10.1109/TNANO.2013.228642410.1109/TNANO.2013.2286424 ↗
32. 10.1109/IJCNN.2017.796630010.1109/IJCNN.2017.7966300 ↗
33. 10.1109/JPROC.2016.259715210.1109/JPROC.2016.2597152 ↗
34. 10.1109/TVLSI.2008.200881010.1109/TVLSI.2008.2008810 ↗
35. 10.1109/ICNN.1994.37453810.1109/ICNN.1994.374538 ↗
36. 10.1109/TCAD.2015.239443410.1109/TCAD.2015.2394434 ↗
37. 10.7873/DATE.2015.061810.7873/DATE.2015.0618 ↗
38. 10.1109/JETCAS.2016.252873910.1109/JETCAS.2016.2528739 ↗
39. 10.1088/2399-1984/aa954a10.1088/2399-1984/aa954a ↗
40. The MNIST database of handwritten digits
41. A circuit-based neural network with hybrid learning of backpropagation and random weight change algorithms
42. 10.1088/0268-1242/27/6/06501010.1088/0268-1242/27/6/065010 ↗
43. 10.1109/TCSI.2018.286651010.1109/TCSI.2018.2866510 ↗
44. 2019
45. 10.1109/IPFA.2011.599279410.1109/IPFA.2011.5992794 ↗
46. 2012
47. 10.1038/s41565-018-0302-010.1038/s41565-018-0302-0 ↗