A Survey of Majority Logic Designs in Emerging Nanotechnologies for Computing

Tingting Zhang; Honglan Jiang; Weiqiang Liu; Fabrizio Lombardi; Leibo Liu; Seok-Bum Ko; Jie Han

doi:10.1109/tnano.2023.3326199

journal article·2023

A Survey of Majority Logic Designs in Emerging Nanotechnologies for Computing

Tingting Zhang, Honglan Jiang, Weiqiang Liu, Fabrizio Lombardi, Leibo Liu, Seok-Bum Ko, Jie Han

IEEE Transactions on Nanotechnology· Volume 22

Publisher page

Source abstract

Abstract

As Moore's law is coming to an end, research on technologies alternative to the complementary metal-oxide semiconductor (CMOS) has been extensively pursued over the last few decades. Many emerging nanotechnologies assemble circuits based on majority logic. It is generally known that majority logic is more expressive and hardware efficient than Boolean logic, however majority logic presents unique challenges at many levels such as arithmetic design and synthesis. With the rediscovery of majority logic as a computational primitive in the post-CMOS era, this paper briefly reviews recent studies from various perspectives to highlight accomplishments and open problems across many domains of majority logic design.

Source: openalex_inverted_index · Quality: baseline

Research context

Nanomaterials Electronic materials

OpenAlex topics: Quantum-Dot Cellular Automata · Advancements in Semiconductor Devices and Circuit Design · Low-power high-performance VLSI design

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

Affiliations

Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada

Department of Micro-Nano Electronic, Shanghai Jiao Tong University, Shanghai, China

College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, China

Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA

Institute of Microelectronics, Beijing National Research Center for Information Science and Technology, Tsinghua University, Beijing, China

Department of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, SK, Canada

Funding

Ph.D. scholarship from the China Scholarship Council · NSF · Natural Sciences and Engineering Research Council of Canada · National Natural Science Foundation of China

References (86)

Show source-provided references

1. 10.1109/TNANO.2002.80738010.1109/TNANO.2002.807380 ↗

2. 10.1109/TNANO.2012.222056510.1109/TNANO.2012.2220565 ↗

3. 10.1109/TNANO.2003.82081510.1109/TNANO.2003.820815 ↗

4. 10.1109/TNANO.2007.89483910.1109/TNANO.2007.894839 ↗

5. Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10 nm CMOS

6. 10.1109/WiSPNET.2016.756621910.1109/WiSPNET.2016.7566219 ↗

7. 10.1109/TNANO.2010.204124810.1109/TNANO.2010.2041248 ↗

8. 10.1117/1.JNP.14.03601110.1117/1.JNP.14.036011 ↗

9. 10.23919/DATE.2018.834223710.23919/DATE.2018.8342237 ↗

10. 10.1049/iet-cds.2016.025210.1049/iet-cds.2016.0252 ↗

11. 10.1109/TNANO.2011.215800610.1109/TNANO.2011.2158006 ↗

12. 10.1007/978-3-030-98347-5_610.1007/978-3-030-98347-5_6 ↗

13. 10.3390/mi1105049610.3390/mi11050496 ↗

14. 10.1109/ETS.2013.656937010.1109/ETS.2013.6569370 ↗

15. 10.1109/TNANO.2019.292283810.1109/TNANO.2019.2922838 ↗

16. 10.1145/296761210.1145/2967612 ↗

17. 10.1109/TNANO.2003.80850710.1109/TNANO.2003.808507 ↗

18. 10.3390/jlpea1003002810.3390/jlpea10030028 ↗

19. 10.1109/TCAD.2018.278978210.1109/TCAD.2018.2789782 ↗

20. Exact synthesis for logic synthesis applications with complex constraints

21. 10.1109/TC.2018.288124510.1109/TC.2018.2881245 ↗

22. 10.1137/S009753979528861110.1137/S0097539795288611 ↗

23. Inversion optimization in majority-inverter graphs

24. 10.1109/TCAD.2023.325708210.1109/TCAD.2023.3257082 ↗

25. 10.1109/ISCAS.2019.870214110.1109/ISCAS.2019.8702141 ↗

26. 10.1109/TNANO.2005.85861110.1109/TNANO.2005.858611 ↗

27. 10.1109/TCAD.2019.289770410.1109/TCAD.2019.2897704 ↗

28. 10.1109/TNANO.2002.80739310.1109/TNANO.2002.807393 ↗

29. An $o(nlogn$) sorting network

30. 10.1109/ACCESS.2022.322920510.1109/ACCESS.2022.3229205 ↗

31. 10.1109/ISVLSI.2017.3710.1109/ISVLSI.2017.37 ↗

32. 10.1109/TVLSI.2020.299736910.1109/TVLSI.2020.2997369 ↗

33. A novel design for quantum-dot cellular automata cells and full adders10.3923/jas.2007.3460.3468 ↗

34. 10.1038/s41598-017-17954-210.1038/s41598-017-17954-2 ↗

35. 10.1109/TNANO.2012.220796510.1109/TNANO.2012.2207965 ↗

36. 10.1126/science.112050610.1126/science.1120506 ↗

37. 10.1109/TNANO.2004.83417710.1109/TNANO.2004.834177 ↗

38. 10.1063/5.001932810.1063/5.0019328 ↗

39. 10.1109/TNANO.2011.211146010.1109/TNANO.2011.2111460 ↗

40. 10.1109/TCSI.2020.304472810.1109/TCSI.2020.3044728 ↗

41. 10.1109/TC.2015.250656610.1109/TC.2015.2506566 ↗

42. 10.1109/TNANO.2007.91520310.1109/TNANO.2007.915203 ↗

43. 10.1109/TNANO.2005.85125110.1109/TNANO.2005.851251 ↗

44. 10.1109/NANO54668.2022.992876810.1109/NANO54668.2022.9928768 ↗

45. 10.3850/9783981537079_028110.3850/9783981537079_0281 ↗

46. 10.1109/TNANO.2018.283691810.1109/TNANO.2018.2836918 ↗

47. 10.1145/2744769.274480610.1145/2744769.2744806 ↗

48. 10.1109/TCSI.2019.291824110.1109/TCSI.2019.2918241 ↗

49. 10.1145/3316781.331790510.1145/3316781.3317905 ↗

50. 10.1109/TCAD.2017.266405910.1109/TCAD.2017.2664059 ↗

51. 10.1109/NANO.2013.672085810.1109/NANO.2013.6720858 ↗

52. Majority logic-based approximate recording adders for high-radix booth multipliers

53. 10.1109/TNANO.2009.202860910.1109/TNANO.2009.2028609 ↗

54. 10.1109/TNANO.2022.314536210.1109/TNANO.2022.3145362 ↗

55. 10.1109/VLSID.2017.2710.1109/VLSID.2017.27 ↗

56. 10.1016/j.micpro.2019.10296210.1016/j.micpro.2019.102962 ↗

57. 10.1109/TNANO.2015.240833010.1109/TNANO.2015.2408330 ↗

58. 10.1007/s00542-017-3587-210.1007/s00542-017-3587-2 ↗

59. 10.1016/j.compeleceng.2020.10656210.1016/j.compeleceng.2020.106562 ↗

60. 10.1016/B978-0-12-812311-9.00001-310.1016/B978-0-12-812311-9.00001-3 ↗

61. 10.1109/ASPDAC.2017.785831210.1109/ASPDAC.2017.7858312 ↗

62. 10.1145/3232195.323220210.1145/3232195.3232202 ↗

63. 10.1109/PGEC.1964.26383010.1109/PGEC.1964.263830 ↗

64. Computer arithmetic: Algorithms and hardware designs

65. 10.1109/NANOARCH47378.2019.18128110.1109/NANOARCH47378.2019.181281 ↗

66. Some schemes for parallel multipliers

67. 10.1145/1117201.111720710.1145/1117201.1117207 ↗

68. 10.1109/ASICON52560.2021.962034410.1109/ASICON52560.2021.9620344 ↗

69. 10.1109/PGEC.1963.26353110.1109/PGEC.1963.263531 ↗

70. 10.1109/TC.2012.14610.1109/TC.2012.146 ↗

71. 10.1109/TCAD.2015.248848410.1109/TCAD.2015.2488484 ↗

72. 10.1145/3489517.353046110.1145/3489517.3530461 ↗

73. 10.1109/12.86303910.1109/12.863039 ↗

74. 10.1109/TNANO.2005.85860910.1109/TNANO.2005.858609 ↗

75. 10.1109/TETC.2019.292910010.1109/TETC.2019.2929100 ↗

76. 10.1109/TC.2009.2110.1109/TC.2009.21 ↗

77. 10.1109/JPROC.2018.286976010.1109/JPROC.2018.2869760 ↗

78. 10.1109/TVLSI.2022.321025210.1109/TVLSI.2022.3210252 ↗

79. 10.1109/ICM.2000.88482810.1109/ICM.2000.884828 ↗

80. 10.1109/TCSII.2021.307766910.1109/TCSII.2021.3077669 ↗

81. 10.1109/ACSSC.2004.139937410.1109/ACSSC.2004.1399374 ↗

82. LUT mapping and optimization for majority-inverter graphs

83. 10.1109/ICVD.2005.15710.1109/ICVD.2005.157 ↗

84. 10.1007/s00034-022-02014-610.1007/s00034-022-02014-6 ↗

85. 10.1109/ISCAS.2018.835096210.1109/ISCAS.2018.8350962 ↗

86. 10.1109/ISCAS.2017.805081910.1109/ISCAS.2017.8050819 ↗