Design Space of Negative Capacitance in FETs
Source abstract
Abstract
Relying on the previously developed charge-based approaches, this paper presents a physics-based design space of negative capacitance in double-gate and bulk MOSFET architectures. The impact of thickness variation of the ferroelectric on the DC characteristics has been deeply investigated. The model precisely estimates a critical thickness of ferroelectric at instability conditions before the device goes into the hysteresis regime. Explicit relationships have been driven for hysteresis voltages which can be used as a general guideline for technology optimization of negative capacitance FETs.
Source: openalex_inverted_index · Quality: baseline
Research context
OpenAlex topics: Ferroelectric and Negative Capacitance Devices · Semiconductor materials and devices · MXene and MAX Phase Materials
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran
Electron Device Modeling and Technology Laboratory (EDLAB) of the École Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland
References (38)
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