Novel Design Methodologies for CNFET-Based Ternary Sequential Logic Circuits

The quest for efficient technologies beyond the traditional CMOS (Complementary-Metal-Oxide-Semiconductor) technology has led researchers to explore newer technologies like the CNFET(Carbon-Nanotube-Field-Effect-Transistor). CNFETs are being used to design and implement various ternary logic circuits. Multivalued logic (MVL) requires multiple threshold voltages that are possible to obtain using CNFETs by modifying the physical dimensions of their CNTs (Carbon Nano Tubes). The ternary sequential logic circuits like ternary D-latch, D-flipflop, and counters existing in literature have been implemented either using STIs (Standard Ternary Inverters) or successor-predecessor circuits. This paper proposes a new design methodology for a ternary D-flipflop that uses a ternary buffer and two STIs designed using two power supplies. Two hybrid architectures for ternary D-flipflop designs have also been proposed that are implemented using a combination of ternary buffer, STIs and successor-predecessor circuits. Using these ternary D-flipflop designs, ternary 3- trit synchronous and asynchronous counters are designed in this paper. The proposed designs are simulated using HSPICE and a standard Stanford CNFET model. The proposed ternary D-flipflops show an improvement of up to 93.5% in power, up to 44.7% in delay and up to 94.3% in PDP compared to existing designs.