Design of a Ternary Memory Cell Using CNTFETs

This paper presents a novel design of a ternary memory cell using carbon nanotube field-effect transistors (CNTFETs). Ternary logic is a promising alternative to conventional binary logic because it allows simplicity and energy efficiency in modern digital design due to the reduced circuit overhead in interconnects and chip area. In this paper, a novel design of a ternary memory cell based on CNTFETs is proposed; this cell uses a transmission gate for the write operation and a buffer for the read operation to make them separate. Chirality of the CNTFETs is utilized for threshold voltage control, thus avoiding the use of additional power supplies. Extensive simulation results using SPICE are reported to show that the two memory operations of the proposed ternary cell perform correctly at 0.9 V power supply. The static noise margin and read/write delay of the proposed ternary memory cell are also very good; by utilizing the latest CNTFET layout design tools, it is shown that the proposed ternary memory cell achieves a significant saving in area (41.6%) compared with its CMOS ternary counterpart at 32 nm.