Board-Level Reliability of 100 × 100 mm Large Glass Packages: Warpage and Thermomechanical Reliability for AI/HPC Applications

With the increasing demand for high-performance semiconductors in the AI era, glass substrates have emerged as a superior alternative due to their exceptional stability, scalability, and smooth surface. Their excellent dimensional stability and smoothness enable ultra-fine line packaging and large-area packages exceeding 100 mm × 100 mm, overcoming the limitations of traditional organic substrates. However, as substrate sizes increase and thickness decreases, challenges related to warpage and thermo-mechanical reliability become critical, particularly for the first-level (chip-on-substrate) and second-level (package-on-PCB) interconnects. While glass substrates can be tailored with an intermediate coefficient of thermal expansion (CTE), reliability concerns persist, both with and without underfill. Despite these advantages, research on the reliability of large-area glass substrate reliability remains limited. This study evaluates the warpage characteristics and board-level reliability of large-area glass substrate packages assembled on PCBs through experiments and modeling. Test vehicles (100 mm × 100 mm) using glass substrate were fabricated with 7,405 SAC305 solder balls and assembled onto PCBs. Shadow moiré was used to measure warpage, while thermal shock cycling tests were conducted to assess interconnect reliability. A finite-element analysis (FEA) framework was developed to determine the process-induced warpage and accumulated inelastic strain during thermal shock cycling. By comparing experimental and simulation results, this study assesses the reliability of second-level interconnects for next-generation AI/HPC packaging architectures.