Estimation of Simultaneous Switching Noise From Frequency-Domain Impedance Response of Resonant Power Distribution Networks
Source abstract
Abstract
Simultaneous switching noise can significantly impact the performance of high-speed systems and needs to be accurately analyzed. The simulation program with integrated circuit emphasis (SPICE) transient simulation with transistor circuits, packages, and boards is the most accurate method but may require a huge computer resource and a long simulation time. Hence, an estimation method of the simultaneous switching noise from the frequency-domain impedance of power distribution networks was presented in this paper. The estimation method can quickly but still accurately calculate the simultaneous switching noise. The estimation method is validated by SPICE transient simulations with transistor models for both the terminated and unterminated systems. In high-speed systems, the difference between the estimation and the worst noise of the transient simulations is less than 20%.
Source: openalex_inverted_index · Quality: baseline
Research context
OpenAlex topics: Electromagnetic Compatibility and Noise Suppression · Electrostatic Discharge in Electronics · Electromagnetic Compatibility and Measurements
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
References (15)
Show source-provided references
1. 10.1109/96.49603810.1109/96.496038 ↗
2. An analytical model of simultaneous switching noise in CMOS systems10.1109/6040.826763 ↗
3. Simulation of lossy package transmission lines using extracted data from one-port TDR measurements and nonphysical RLGC models10.1109/TADVP.2005.849563 ↗
4. Estimation of simultaneous switching noise from power distribution network impedance in LPDDR2 systems
5. 10.1109/EPEP.2002.105790910.1109/EPEP.2002.1057909 ↗
6. 10.1109/TADVP.2008.200220110.1109/TADVP.2008.2002201 ↗
7. 10.1109/96.53388510.1109/96.533885 ↗
8. 10.1109/96.61822910.1109/96.618229 ↗
9. 10.1109/EPEP.2007.438715910.1109/EPEP.2007.4387159 ↗
10. Study of signal and power integrity challenges in high-speed memory I/O designs using single-ended signaling schemes
11. 10.1109/96.67370310.1109/96.673703 ↗
12. hair · Power Integrity Analysis and Management for Integrated Cirucits · 2010
13. 10.1109/TEMC.2010.204538210.1109/TEMC.2010.2045382 ↗
14. 10.1109/4.9899510.1109/4.98995 ↗
15. 10.1109/EPEP.2004.140759410.1109/EPEP.2004.1407594 ↗