journal article·2021-05

Temperature analysis on electrostatics performance parameters of dual metal gate step channel TFET

Sachin Kumar, Dharmendra Singh Yadav

Applied Physics A· Volume 127· Issue 5
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Abstract

In this research work, a device structure modification for a doped tunnel field-effect transistor (TFET) is proposed with gate engineering at the gate electrode to overcome the limitations of conventional TFET. Moreover, the temperature is one of the most effective parameters which affects the device performance. In this concern, a brief research of temperature impact on DC characteristics, analog/RF parameter, and linearity parameters has been performed for the proposed device at temperatures ranging from 250K to 400K with an interval of 50K. OFF-state current is more sensitive towards high temperature which results in high ambipolar behavior due to thermal leakage current which degrades switching speed. So, the impact of temperature on output current at low applied voltages is also studied using different models like BTBT, SRH, and TAT. However, ON-state current shows a negligible impact of temperature variation that makes a very prominent device for low-power high-frequency applications. This type of detailed study on all the performance parameters of the proposed device is beneficial from a design point of view.
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Research context

OpenAlex topics: Advancements in Semiconductor Devices and Circuit Design · Semiconductor materials and devices · Ferroelectric and Negative Capacitance Devices

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References (33)

Show source-provided references
1. Sah Chih-Tang, Evolution of the MOS transistor-from conception to VLSI. Proc. IEEE 76(10), 1280–1326 (1988)10.1109/5.16328 ↗
2. S.W. Sun, P.G.Y. Tsui, Limitation of CMOS supply-voltage scaling by MOSFET threshold-voltage variation. IEEE J. solid-State Circuits 30(8), 947–949 (1995)10.1109/4.400439 ↗
3. Hiroshi Iwai, CMOS technology-year 2010 and beyond. IEEE J. Solid-State Circuits 34(3), 357–366 (1999)10.1109/4.748187 ↗
4. Woo Young Choi, B.G. Park, J.D. Lee, T.J.K. Liu, Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28(8), 743–745 (2007)10.1109/LED.2007.901273 ↗
5. Lu. Nian Liu, Jie Zhao Zhenda, Matthew T. McDowell, H.W. Lee, W. Zhao, Y.I. Cui, A pomegranate-inspired nanoscale design for large-volume-change lithium battery anodes. Nat. Nanotechnol. 9(3), 187 (2014)10.1038/nnano.2014.6 ↗
6. S.M. Turkane, A.K. Kureshi, Review of tunnel field effect transistor (TFET). Int. J. Appl. Eng. Res. 11(7), 4922–4929 (2016)
7. Yan Zhu, Mantu K. Hudait, Low-power tunnel field effect transistors using mixed As and Sb based heterostructures. Nanotechnol. Rev. 2(6), 637–678 (2013)10.1515/ntrev-2012-0082 ↗
8. M. Sneh Saurabh, J. Kumar, Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Trans. Electron Devices 58(2), 404–410 (2010)10.1109/TED.2010.2093142 ↗
9. Jaya Madan, Rishu Chaujar, Gate drain underlapped-PNIN-GAA-TFET for comprehensively upgraded analog/RF performance. Superlattices Microstruct. 102, 17–26 (2017)10.1016/j.spmi.2016.12.034 ↗
10. B. Dawit, M. Abdi, Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain. IEEE J. Electron Devices Soc. 2(6), 187–190 (2014)10.1109/JEDS.2014.2327626 ↗
11. Kathy Boucart, A.M. Ionescu, Double-gate tunnel FET with high-$$\kappa$$ gate dielectric. IEEE Trans. Electron Devices 54(7), 1725–1733 (2007)10.1109/TED.2007.899389 ↗
12. D..S.. yadav, D. Sharma, B.R. Raad, V. Bajaj, Dharmendra Singh Yadav, Impactful study of dual work function, underlap and hetero gate dielectric on TFET with different drain doping profile for high frequency performance estimation and optimization. Superlattices Microstruct. 96, 36–46 (2016)10.1016/j.spmi.2016.04.027 ↗
13. D.S. Yadav, B.R. Raad, D. Sharma, Dharmendra Singh Yadav, A novel gate and drain engineered charge plasma tunnel field-effect transistor for low sub-threshold swing and ambipolar nature. Superlattices Microstruct. 100, 266–273 (2016)10.1016/j.spmi.2016.09.029 ↗
14. U.E. Avci, I.A. Young, ”Heterojunction TFET scaling and resonant-TFET for steep subthreshold slope at sub-9nm gate-length.” In 2013 IEEE International Electron Devices Meeting, pp. 4-3. IEEE, (2013)10.1109/IEDM.2013.6724559 ↗
15. D.S. Yadav, D. Sharma, S. Tirkey, D. Soni, D.G. Sharma, S. Bajpai, N. Sharma, ”A comparative study of GaP/SiGe hetero junction double gate tunnel field effect transistor.” In 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), pp. 195-199. IEEE, (2017)10.1109/iNIS.2017.48 ↗
16. Sukeshni Tirkey, Dheeraj Sharma, B.R. Raad, D.S. Yadav, A novel approach to improve the performance of charge plasma tunnel field-effect transistor. IEEE Trans. Electron Devices 65(1), 282–289 (2017)10.1109/TED.2017.2766262 ↗
17. Saeed Nosohiyan, H.R. Ebrahimi, A.A. Nourbakhsh, G.R. Amiri, Synthesis, characterization, and sensing performance investigation of nickel ferrite nanoparticles for ammonia detection. IEEE Trans. Magn. 55(12), 1–6 (2019)10.1109/TMAG.2019.2935054 ↗
18. H.R. Ebrahimi, H. Emami, G.R. Amiri, Hamid Reza Ebrahimi, Synthesis, characterization, and sensing performance investigation of copper cadmium ferrite nanoparticles. IEEE Trans. Magn. 54(10), 1–5 (2018)10.1109/TMAG.2018.2852749 ↗
19. H.R. Ebrahimi, M.H. Soureshjani, B. Bahraminejad, Highly sensitive Ni0. 5Cu0. 5Fe2O4 nano particles as an ethanol gas sensor. Sens. Lett. 14(2), 205–209 (2016)10.1166/sl.2016.3585 ↗
20. S. Kumar, D. S. Yadav, S. Saraswat, N. Parmar, R. Sharma, A. Kumar, ”A novel step-channel TFET for better subthreshold swing and improved analog/RF characteristics.” In 2020 IEEE International Students’ Conference on Electrical, Electronics and Computer Science (SCEECS), pp. 1-6. IEEE, (2020)10.1109/SCEECS48394.2020.104 ↗
21. M. R. Tripathy, A. K. Singh, K. Baral, P. K. Singh, A. K. Mishra, D. K. Jarwal, S. Jit, ”Study of temperature sensitivity on linearity figures of merit of Ge/Si hetero-junction gate-drain underlapped vertical tunnel FET with heterogeneous gate dielectric structure for improving device reliability.” In 2020 URSI Regional Conference on Radio Science (URSI-RCRS), pp. 1-4. IEEE, (2020)10.23919/URSIRCRS49211.2020.9113520 ↗
22. T. Nirschl, P.F. Wang, W. Hansch, D. Schmitt-Landsiedel, ”The tunnelling field effect transistors (TFET): the temperature dependence, the simulation model, and its application.” In 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No. 04CH37512), vol. 3, pp. III-713. IEEE, (2004)
23. Quentin Smets, Anne S. Verhulst, Eddy Simoen, David Gundlach, Curt Richter, Nadine Collaert, Marc M. Heyns, Calibration of bulk trap-assisted tunneling and ShockleyReadHall currents and impact on InGaAs tunnel-FETs. IEEE Trans. Electron Devices 64(9), 3622–3626 (2017)10.1109/TED.2017.2724144 ↗
24. F.S. Neves, P.G.D. Agopian, J.A. Martino, B. Cretu, R. Rooyackers, A. Vandooren, E. Simoen, A. Voon-Yew Thean, C. Claeys, Low-frequency noise analysis and modeling in vertical tunnel FETs with Ge source. IEEE Trans. Electron Devices 63(4), 1658–1665 (2016)10.1109/TED.2016.2533360 ↗
25. R. Narang, M. Saxena, R.S. Gupta, M. Gupta, Impact of temperature variations on the device and circuit performance of tunnel FET: a simulation study. IEEE Trans. Nanotechnol. 12(6), 951–957 (2013)10.1109/TNANO.2013.2276401 ↗
26. A.B. Sproul, M.A. Green, Improved value for the silicon intrinsic carrier concentration from 275 to 375 K. J. Appl. Phys. 70(2), 846–854 (1991)10.1063/1.349645 ↗
27. J. Knoch, J. Appenzeller. ”A novel concept for field-effect transistors-the tunneling carbon nanotube FET.” In 63rd Device Research Conference Digest, 2005. DRC’05., vol. 1, pp. 153-156. IEEE, (2005)10.1109/DRC.2005.1553099 ↗
28. D. S. Yadav, D. Sharma, R. Agrawal, G. Prajapati, S. Tirkey, B. R. Raad, V. Bajaj, ”Temperature based performance analysis of doping-less tunnel field effect transistor.” In 2017 International Conference on Information, Communication, Instrumentation and Control (ICICIC), pp. 1-6. IEEE, (2017)10.1109/ICOMICON.2017.8279131 ↗
29. D. Agopian, P. Ghedini, M.D.V. Martino, S.G.D.S. Filho, J.A. Martino, R. Rooyackers, D. Leonelli, C. Claeys, Temperature impact on the tunnel FET off-state current components. Solid-State Electron. 78, 141–146 (2012)10.1016/j.sse.2012.05.053 ↗
30. G.A. M. Hurkx, D.B.M. Klaassen, M.P.G. Knuvers, F.G. O’hara. ”A new recombination model describing heavy-doping effects and low-temperature behaviour.” In International Technical Digest on Electron Devices Meeting, pp. 307-310. IEEE, (1989)
31. P.K. Verma, S.K. Gupta, ”Proposal of charge plasma based recessed source/drain dopingless junctionless transistor and its linearity distortion analysis for circuit applications.” Silicon : 1-28 (2020)10.1007/s12633-020-00402-8 ↗
32. R. Narang, M. Saxena, R.S. Gupta, M. Gupta, Linearity and analog performance analysis of double gate tunnel FET: effect of temperature and gate stack. Int. J. VLSI Design Commun. Syst. 2(3), 185 (2011)10.5121/vlsic.2011.2316 ↗
33. Emona Datta, Avik Chattopadhyay, Abhijit Mallik, Yasuhisa Omura, Temperature dependence of analog performance, linearity, and harmonic distortion for a ge-source tunnel FET. IEEE Trans. Electron Devices 67(3), 810–815 (2020)10.1109/TED.2020.2968633 ↗