Impact of gate overlap and underlap on analog/RF and linearity performance of dual-material gate-oxide-stack double-gate TFET
Source abstract
Abstract
The work presented here, investigates the effect of overlap and underlap extensively on dual-material gate-oxide-stack double-gate tunnel field effect transistor (DMGOSDG-TFET) for the first time. To observe the influence of overlap and underlap on the device performance, DC parameters and analog/RF parameters such as: transfer characteristics, parasitic capacitances, transconductance ((gm)), cutoff frequency ((f_T)), Gain Bandwidth Product (GBP) for DMGOSDG-TFET with overlap and underlap have been inspected and analyzed in contrast with the conventional device dual-material double-gate tunnel field effect transistor (DMDG-TFET) with similar dimension. Along with this, the impact of overlap and underlap on linearity parameters such as Input Intercept Point ((mathrm {IIP}_3)), Intermodulation Point ((mathrm {IMD}_3)) and Voltage Intercept Point ((mathrm {VIP}_3)) have been also investigated and contrasted with the conventional DMDG-TFET. The impact of positive and negative trap charges has also been carried out in this work for the (I_mathrm {DS}-V_mathrm {GS}) characteristics of devices. Along with this, the gate leakage has also been studied. The TCAD simulation results prove that DMGOSDG-TFET is a better candidate where DC, analog/RF and linearity performance would be of great importance under overlap and underlap conditions. The simulation results also demonstrate that gate to source overlap and underlap, improves the device performance and makes the device more reliable for analog/RF applications. However, increasing the overlapping beyond 5nm does not bring any further enhancement in the device performance.
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Research context
OpenAlex topics: Advancements in Semiconductor Devices and Circuit Design · Semiconductor materials and devices · Integrated Circuits and Semiconductor Failure Analysis
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
References (45)
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1. R.H. Yan, O. Abbas, K.F. Lee, Scaling the Si MOSFET: from bulk to SOI to bulk. IEEE Trans. Electron Devices 39(7), 1704–1710 (1992)10.1109/16.141237 ↗
2. K.K. Young, Short-channel effect in fully-depleted SOI MOSFETs. IEEE Trans. Electron Devices 36(2), 399–402 (1989)10.1109/16.19942 ↗
3. S. Bangsaruntip, G.M. Cohen, A. Majumdar, J.W. Sleight, Universality of short-channel effects in undoped-body silicon nanowire MOSFETs. IEEE Trans. Electron Devices 31(9), 903–905 (2010)10.1109/LED.2010.2052231 ↗
4. P. Verma, S. Kumar, K. Nigam, Performance Analysis of Stack Gate Oxide Underlap TFET Utilising Metal Strip Mechanism, International Conference on Signal Processing and Communication (ICSC), 372-376 (2021)10.1109/ICSC53193.2021.9673444 ↗
5. Y. Cui, Z. Zhong, D. Wang, W.U. Wang, C.M. Lieber, Nano Lett. 3(2), 149–152 (2003)10.1021/nl025875l ↗
6. S. Kumar, K.S. Singh, K. Nigam, Dual-material dual-oxide double-gate TFET for improvement in DC characteristics, analog/RF and linearity performance. Appl. Phys. A 125(5), 353–360 (2019)10.1007/s00339-019-2650-5 ↗
7. A. Raj, S. Singh, K.N. Priyadarshani, A. Naugarhiya, Vertically extended drain double gate $$Si{1-x}Gex$$ source tunnel FET : proposal & investigation for optimized device performance. Silicon 13, 2589–2604 (2020)10.1007/s12633-020-00603-1 ↗
8. J. Talukdar, K. Mummaneni, A non-uniform silicon TFET design with dual-material source and compressed drain. Appl. Phys. A (2020). https://doi.org/10.1007/s00339-019-3266-510.1007/s00339-019-3266-5 ↗
9. Km. S. Singh, S. Kumar, K. Nigam, Impact of interface trap charges on analog/RF and linearity performances of dual-material gate-oxide-stack double-gate TFET. IEEE Transact. Device Mater. Reliab. 20(2), 404–412 (2020)10.1109/TDMR.2020.2984669 ↗
10. K.M. Liu, C.P. Cheng, Investigation on the Effects of Gate/Source Overlap/Underlap and Source Doping Gradient of n-Type Si Cylindrical Gate-All-Around Tunnel-Field Transistors. IEEE Trans. Nanotechnol. 23(19), 382–389 (2020)10.1109/TNANO.2020.2991787 ↗
11. G. Wadhva, B. Raj, Parametric Variation Analysis of Symmetric Double Gate Charge Plasma JLTFET for Biosensor Application. IEEE Sens. J. 18(15), 6070–6077 (2018)10.1109/JSEN.2018.2846409 ↗
12. A.M. Walke, W.G. Vandenberghe, K.H. Kao, A. Vanooren, G. Groenseneken, A Simulation Study on Process Sensitivity of Line Tunnel Field-Effect Transistor. IEEE Trans. Electron Devices 60(3), 1019–1027 (2013)10.1109/TED.2013.2242201 ↗
13. S. Yadav, A. Lemtur, D. Sharma, M. Aslam, D. Soni, Effective approach to enhance DC and high-frequency performance of electrically doped TFET. Micro Nano Lett. 13(10), 1469–1474 (2018)10.1049/mnl.2018.5072 ↗
14. K. Nigam, S. Pandey, P. Kondekar, D. Sharma, P.K. Parte, A Barrier Controlled Charge Plasma-Based TFET With Gate Engineering for Ambipolar Suppression and RF/Linearity Performance Improvement. IEEE Trans. Electron Devices 64(6), 2751–2757 (2017)10.1109/TED.2017.2693679 ↗
15. K. Nigam, P.N. Kondekar, D. Sharma, DC characteristics and analog/RF performance of novel polarity control GaAs-Ge based tunnel field effect of transistor. Superlattices Microstruct. 92, 224–231 (2016)10.1016/j.spmi.2016.01.032 ↗
16. S. Kumar, S. Singh, K. Nigam, V.A. Tikkiwal, Dual material dual-oxide dual gate TFET for improvement in DC characteristics, analog/RF and linearity performance. Appl. Phys. A 125(5), 3531–3538 (2019)10.1007/s00339-019-2650-5 ↗
17. T. Joshi, Y. Singh, B. Singh, Extended-Source Double-Gate Tunnel FET With Improved DC and Analog/RF Performance. IEEE Trans. Electron Devices 67(4), 1873–1879 (2020)10.1109/TED.2020.2973353 ↗
18. P.N. Kondekar, K. Nigam, S. Pandey, D. Sharma, Design and analysis of polarity controlled electrically doped tunnel FET with bandgap engineering for analog/RF applications. IEEE Trans. Electron Devices 64(2), 412–418 (2017)10.1109/TED.2016.2637638 ↗
19. N. Mohankumar, B. Syamal, C.K. Sarkar, Influence of channel and gate engineering on the analog and RF performance of DG MOSFETs. IEEE Trans. Electron Devices 57(4), 820–826 (2010)10.1109/TED.2010.2040662 ↗
20. K. Dharmender, Nigam, Low-K Dielectric Pocket and Workfunction Engineering for DC and Analog/RF Performance Improvement in Dual Material Stack Gate Oxide Double Gate TFET. Silicon (2020). https://doi.org/10.1007/s12633-020-00822-610.1007/s12633-020-00822-6 ↗
21. S. Kumar, Temperature dependence of analogue/RF performance, linearity and harmonic distortion for dual-material gate-oxide-stack double-gate TFET. IET Circuits Devices Syst. 15(6), 540–552 (2020)10.1049/cds2.12049 ↗
22. K. Vanlalawmpuia, R. Saha, B. Bhowmick, Performance evaluation of hetero-stacked TFET for variation in lateral straggle and its application as digital inverter. Appl. Phys. A 124(10), 701–712 (2018)10.1007/s00339-018-2121-4 ↗
23. S. Ashish, D. Sharma, Y.B.N. Kumar, M.H. Vasantha, Performance Enhancement of Novel InAs/Si hetero double-gate Tunnel FET. IEEE Transactions Electron Devices 63(1), 288–295 (2016)10.1109/TED.2015.2503141 ↗
24. A.M. Jossy, S.S. Kumar, A. Chakraborty, N. Lahiri, Design Optimization Of Triple Material Gate Stacked Oxide TFET. Int. J. Recent Technol. Eng. 7(6), 1947–1950 (2019)
25. W. Cao, J. Jiang, J. Kang, D. Sarkar, W. Liu, K. Banerjee, Designing band-to-band tunneling field-effect transistors with 2D semiconductors for next-generation low-power VLSI. IEEE Int. Electron Devices Meeting 10, 12.3.1-12.3.4 (2015)
26. D. Kumar, R.G. Mishra, R. Mishra, A.K. Srivastava, Impact of band to band Tunneling on Transient performance of Dual Gate Tunnel Field Effect Transistor (TFET). IJITEE 8(9), 284–288 (2019)10.35940/ijitee.H7236.078919 ↗
27. W.G. Vandenberghe, B. Soree, W. Magnus, M.V. Fischett, A.S. Verhulst, G. Groeseneken, Two-dimensional quantum mechanical modeling of band-to-band tunneling in indirect semiconductors. Int. Electron Devices Meeting 2, 5.3.1-5.3.4 (2011)
28. C. Shen, L.T. Yang, E. Toh, C. Heng, G.S. Samudra, Y. Yeo, A new robust non-local algorithm for band-to-band tunneling simulation and its application to Tunnel-FET. J. Solid-State Electron. 57(1), 23–30 (2011)10.1016/j.sse.2010.10.005 ↗
29. A. Biswas, S.S. Dan, C.L. Royer, W. Grabinski, A.M. Ionescu, TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model. J. Microelectron. Eng. 98, 334–337 (2012)10.1016/j.mee.2012.07.077 ↗
30. S. Chander, O.P. Mahto, V. Chander, S. Baishya, Analysis of novel SGOI-TFET with record low subthreshold swing (SS) and high Ion/Ioff ratio. International Conference on Computing for Sustainable Global Development (INDIACom) 10, 500–504 (2014)
31. K. Boucart, A.M. Ionescu, Double gate tunnel FET with high k gate dielectric. IEEE Trans. Electron Devices 54(7), 1725–1733 (2007)10.1109/TED.2007.899389 ↗
32. J. Madan, R. Chaujar, Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability. IEEE Trans. Device Mater. Reliab. 16(2), 227–234 (2016)10.1109/TDMR.2016.2564448 ↗
33. P. Venkatesh, K. Nigam, S. Pandey, D. Sharma, P.N. Kondekar, Impact of interface trap charges on performance of electrically doped tunnel FET with heterogeneous gate dielectric. IEEE Trans. Device Mater. Reliab. 17(1), 245–252 (2017)10.1109/TDMR.2017.2653620 ↗
34. D. Nishad, K. Nigam, S. Kumar, Temperature Sensitivity Analysis of Extended Source Double Gate Tunnel Field Effect Transistor, Silicon, (2021). https://doi.org/10.21203/rs.3.rs-359321/v110.21203/rs.3.rs-359321/v1 ↗
35. V. Raju, K. Sivasankaran, Performance Analysis of Double Gate Junctionless Tunnel Field Effect Transistor: RF Stability Perspective. Int. J. Adv. Comput. Sci. and Appl. 10(11), 529–537 (2019)
36. S. Kumar, D.S. Yadav, Assessment of Interface Trap Charges on Proposed TFET for Low Power High-Frequency Application, Silicon (2021). https://doi.org/10.21203/rs.3.rs-286208/v110.21203/rs.3.rs-286208/v1 ↗
37. P. Ghosh, S. Haldar, R.S. Gupta, M. Gupta, An Investigation of Linearity Performnace and Intermodulation Distortion of GME CGT MOSFET for RFIC Design. IEEE Transactions Electron Devices 59(12), 3263–3268 (2012)10.1109/TED.2012.2219537 ↗
38. J. Talukdar, G. Rawat, K. Mummaneni, A Novel Extended Source TFET with $$\delta \text{ p}^+$$ - SiGe Layer. Silicon 12, 2273–2281 (2020)10.1007/s12633-019-00321-3 ↗
39. P. Venkatesh, K. Nigam, S. Pandey, D. Sharma, P.N. Kondekar, Impact of Interface Trap Charges on Performance of Electrically Doped Tunnel FET With Heterogeneous Gate Dielectric. IEEE Trans. Device Mater. Reliab. 17(1), 245–252 (2017)10.1109/TDMR.2017.2653620 ↗
40. S. Gupta, K. Nigam, S. Pandey, D. Sharma, P.N. Kondekar, Effect of Interface Trap Charges on Performance Variation of Heterogeneous Gate Dielectric Junctionless-TFET. IEEE Trans. Electron Devices 64(11), 4731–4737 (2017)10.1109/TED.2017.2754297 ↗
41. N. Kumar, A. Raman, Performance Assessment of the Charge-Plasma-Based Cylindrical GAA Vertical Nanowire TFET With Impact of Interface Trap Charges. IEEE Trans. Electron Devices 66(10), 4453–4460 (2019)10.1109/TED.2019.2935342 ↗
42. S. Sharma, R. Basu, B. Kaur, Temperature Analysis of a Dopingless TFET Considering Interface Trap Charges for Enhanced Reliability. IEEE Trans. Electron Devices 69(5), 2692–2697 (2022)10.1109/TED.2022.3156895 ↗
43. K.S. Singh, S. Kumar, K. Nigam, Impact of Interface Trap Charges on Analog/RF and Linearity Performances of Dual-Material Gate-Oxide-Stack Double-Gate TFET. IEEE Trans. Device Mater. Reliab. 20(2), 404–412 (2020)10.1109/TDMR.2020.2984669 ↗
44. A. Shaker, M. ElSabbagh, M.M. El-Banna, Impact of Impact of Nonuniform Gate Oxide Shape on TFET Performance: A Reliability Issue. Physica E 106, 346–351 (2019)10.1016/j.physe.2018.07.001 ↗
45. P. Chaturvedi, M.J. Kumar, Impact of gate leakage considerations in tunnel field effect transistor design, Japanese Journal of Applied Physics, 53(7), 074201-074201-8 (2014)10.7567/JJAP.53.074201 ↗