journal article·2018-01-01Open access

Double-gated ultra-thin-body GaAs-on-insulator p-FETs on Si

Jae-Phil Shim, Seong Kwang Kim, Hansung Kim, Gunwu Ju, Heejeong Lim, SangHyeon Kim, Hyung-jun Kim

APL Materials· Volume 6· Issue 1

Abstract

We demonstrated ultra-thin-body (UTB) junctionless (JL) p-type field-effect transistors (pFETs) on Si using GaAs channels. Wafer bonding and epitaxial lift-off techniques were employed to fabricate the UTB p-GaAs-on-insulator on a Si template. Subsequently, we evaluated the JL FETs having different p-GaAs channel thicknesses considering both maximum depletion width and doping concentration for high performance. Furthermore, by introducing a double-gate operation, we more effectively controlled threshold voltage and attained an even higher ION/IOFF of >106, as well as a low subthreshold swing value of 300 mV/dec.
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Research context

OpenAlex topics: Semiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Nanowire Synthesis and Applications

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Affiliations

Center for Spintronics, Korea Institute of Science and Technology 1 , Seoul 02792, South Korea

Center for Opto-Electronic Materials and Devices, Korea Institute of Science and Technology 2 , Seoul 02792, South Korea

School of Electrical Engineering, Kookmin University 3 , Seoul 02707, South Korea

KU-KIST Graduate School of Converging Science and Technology, Korea University 4 , Seoul 02841, South Korea

Division of Nano and Information Technology, KIST School, Korea University of Science and Technology 5 , Seoul 02792, South Korea

Funding

Future semiconductor device technology development program funded by Ministry of Trade, Industry and Energy · National Research Foundation of Korea

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