Tailing phenomenon in high voltage solid-state pulse modulators: Analyzing and modeling

In many applications of high-voltage solid-state pulse modulators (SSPMs), the expected square pulsed shape is difficult to be generated and also there exists a long falling edge (also known as the “tailing”). In some fields that strictly need squared pulses, tailing will restrict the application of SSPMs. Although topological solutions have been proposed to eliminate the tail, its formation and regulatory factors are still not clear. Based on the classic switch–capacitor circuit, the tailing model is discussed and established for stacked and non-stacked SSPMs in this paper, which can help predict the pulsed tailing of SSPMs under various loads. The circuital factors (stage number, parasitic inductance, etc.) of the pulsed tail are studied. Meanwhile, the suggested tailing criteria for different load scenarios are proposed. The experiment verifies the accuracy of the tailing model. Finally, the applicable conditions of the tailing model are discussed. This model can not only help explain the mechanism of tailing but make predictions of tailing in SSPMs.