A SONOS device with a separated charge trapping layer for improvement of charge injection
Source abstract
Abstract
A charge trapping layer that is separated from the primary gate dielectric is implemented on a FinFET SONOS structure. By virtue of the reduced effective oxide thickness of the primary gate dielectric, a strong gate-to-channel coupling is obtained and thus short-channel effects in the proposed device are effectively suppressed. Moreover, a high program/erase speed and a large shift in the threshold voltage are achieved due to the improved charge injection by the reduced effective oxide thickness. The proposed structure has potential for use in high speed flash memory.
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Research context
OpenAlex topics: Semiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Advanced Memory and Neural Computing
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Affiliations
Kwangwoon University 1 Department of Electronic Engineering, , Seoul 01897, Korea
KAIST 2 School of Electrical Engineering, , 291 Daehak-ro, Daejeon 34141, Korea
National Nanofab Center 3 , 291 Daehak-ro, Daejeon 34141, Korea
Kookmin University 4 School of Electrical Engineering, , 77 Jeongneung-ro, Seongbuk-gu, Seoul 02707, Korea
Funding
Kwangwoon University
References (13)
Show source-provided references
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