Preparation of thin-film SOI wafer by low-dose ion implantation
Source abstract
Abstract
Silicon-on-insulator (SOI) devices have many advantages, such as high speed, low energy consumption, radiation-hard, and high integration. In this paper, the separation by implanted oxygen process under low-dose implantation conditions is studied by the two-step implantation method combined with the internal thermal oxidation process. The effects of different types of silicon wafers and different implantation doses on SOI surface defects, top Si thickness, buried oxide (BOX) layer thickness, BOX layer breakdown voltage, and top Si defect density were investigated. Ultra-thin SOI wafers are prepared by epitaxial silicon wafers and control the first implantation dose. The number of surface defects of SOI materials is less than 100 counts, the breakdown voltage of the BOX layer is about 7.8 MV/cm, and the top Si dislocation density is about 8 × 103 cm−2.
Source: crossref · Quality: baseline
Research context
OpenAlex topics: Semiconductor materials and devices · Integrated Circuits and Semiconductor Failure Analysis · Advancements in Semiconductor Devices and Circuit Design
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
School of Materials Science and Engineering, Hebei University of Technology 1 , Tianjin 300132, China
Zhonghuan Advanced Semiconductor Materials Co., Ltd. 2 , Wuxi 214200, China
Hebei Engineering Laboratory of Photoelectronic Functional Crystals, Hebei University of Technology 3 , Tianjin 300130, China
Funding
Science and Technology Correspondent of Tianjin City · Research Foundation of Education Bureau of Hebei
References (25)
Show source-provided references
1. 2004
2. Silicon-on-insulator processes for the fabrication of novel nanostructures10.1116/1.1404980 ↗
3. SOI technology for MEMS applications
4. Applications of SOI-based optical MEMS10.1109/2944.991410 ↗
5. Effects of grating heights on highly efficient unibond SOI waveguide grating couplers10.1109/68.817493 ↗
6. The pH response of a silicon-on-insulator MOSFET with an integrated nanofluidic cell
7. High-voltage integrated circuits: History, state of the art, and future prospects10.1109/ted.2016.2631125 ↗
8. A high-sensitivity resonant differential pressure microsensor based on bulk micromachining10.1109/jsen.2021.3051286 ↗
9. Design of a 60 GHz 32% PAE class-AB PA with 2nd harmonic control in 45-nm PD-SOI CMOS10.1109/TCSI.2020.2984042 ↗
10. 2020
11. Characterization of crystal structure features of a SIMOX substrate10.1016/j.nimb.2015.08.050 ↗
12. Practical reduction of dislocation density in SIMOX wafers10.1049/el:19901055 ↗
13. Low defect, high quality SIMOX material for bipolar device applications
14. Low energy SIMOX(LES)
15. Design considerations of SOI digital CMOS VLSI
16. Fabrication of device-grade silicon-on-insulator material from appropriate matches of low oxygen implantation dose and acceleration energy10.1116/1.1599859 ↗
17. Technological innovation in low-dose SIMOX wafers fabricated by an internal thermal oxidation (ITOX) process10.1016/s0167-9317(02)00913-9 ↗
18. Surface defects on SOI wafers and their influence on device characteristics10.1002/ecjb.1125 ↗
19. Elimination of square pits on SIMOX wafer by using nitrogen-doped Cz crystal
20. Formation of ultrathin, buried oxides in Si by O+ ion implantation10.1063/1.117802 ↗
21. Defects in separation by implanted oxygen wafer probed by monoenergetic positron beams10.1007/bf00567585 ↗
22. Improvement on the breakdown voltage for silicon-on-insulator devices based on epitaxy-separation by implantation oxygen by a partial buried n+-layer10.1088/1674-1056/21/2/027101 ↗
23. Low-dose SIMOX wafers for LSIs fabricated with internal-thermal-oxidation (ITOX) process: Electrical characterization10.1023/a:1008997423606 ↗
24. 2004
25. Gettering layer for oxygen accumulation in the initial stage of SIMOX processing10.1016/j.nimb.2009.01.029 ↗